\item Convert remaining logic to bit-level logic functions
\item Perform optimizations on bit-level logic functions
\item Map bit-level logic gates and registers to cell library
-\item Write results to output file
+\item Write results to output file
\end{itemize}
\end{frame}
is a macro command that calls other commands:
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-opt_const # const folding
-opt_share -nomux # merging identical cells
+opt_expr # const folding and simple expression rewriting
+opt_merge -nomux # merging identical cells
do
opt_muxtree # remove never-active branches from multiplexer tree
opt_reduce # consolidate trees of boolean ops to reduce functions
- opt_share # merging identical cells
+ opt_merge # merging identical cells
opt_rmdff # remove/simplify registers with constant inputs
opt_clean # remove unused objects (cells, wires) from design
- opt_const # const folding
+ opt_expr # const folding and simple expression rewriting
while [changed design]
\end{lstlisting}
can be used as shortcut for {\tt clean}. For example:
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-proc; opt; memory; opt_const;; fsm;;
+proc; opt; memory; opt_expr;; fsm;;
\end{lstlisting}
\end{frame}
\begin{frame}{\subsecname}
Usually it does not hurt to call {\tt opt} after each regular command in the
synthesis script. But it increases the synthesis time, so it is favourable
-to only call {\tt opt} when an improvement can be archieved.
+to only call {\tt opt} when an improvement can be achieved.
\bigskip
The designs in {\tt yosys-bigsim} are a good playground for experimenting with
\end{frame}
\begin{frame}{\subsecname{} -- details}
-Some details on the most importand commands from the {\tt fsm\_*} group:
+Some details on the most important commands from the {\tt fsm\_*} group:
\bigskip
The {\tt fsm\_detect} command identifies FSM state registers and marks them