kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero

[yosys.git] / manual / PRESENTATION_ExSyn.tex

diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex
index f68b6f984e99a1fe1bec425c165a92628b31043e..655720ebc6482331f8b0e8460382be679bd4e32d 100644 (file)
--- a/manual/PRESENTATION_ExSyn.tex
+++ b/manual/PRESENTATION_ExSyn.tex
@@ -22,7 +22,7 @@
 \item Convert remaining logic to bit-level logic functions
 \item Perform optimizations on bit-level logic functions
 \item Map bit-level logic gates and registers to cell library
-\item Write results to output file 
+\item Write results to output file
 \end{itemize}
 \end{frame}
 
@@ -144,16 +144,16 @@ The {\tt opt} command implements a series of simple optimizations. It also
 is a macro command that calls other commands:
 
 \begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-opt_const               # const folding
-opt_share -nomux        # merging identical cells
+opt_expr                # const folding and simple expression rewriting
+opt_merge -nomux        # merging identical cells
 
 do
     opt_muxtree         # remove never-active branches from multiplexer tree
     opt_reduce          # consolidate trees of boolean ops to reduce functions
-    opt_share           # merging identical cells
+    opt_merge           # merging identical cells
     opt_rmdff           # remove/simplify registers with constant inputs
     opt_clean           # remove unused objects (cells, wires) from design
-    opt_const           # const folding
+    opt_expr            # const folding and simple expression rewriting
 while [changed design]
 \end{lstlisting}
 
@@ -161,7 +161,7 @@ The command {\tt clean} can be used as alias for {\tt opt\_clean}. And {\tt ;;}
 can be used as shortcut for {\tt clean}. For example:
 
 \begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-proc; opt; memory; opt_const;; fsm;;
+proc; opt; memory; opt_expr;; fsm;;
 \end{lstlisting}
 \end{frame}
 
@@ -216,7 +216,7 @@ proc; opt; memory; opt_const;; fsm;;
 \begin{frame}{\subsecname}
 Usually it does not hurt to call {\tt opt} after each regular command in the
 synthesis script. But it increases the synthesis time, so it is favourable
-to only call {\tt opt} when an improvement can be archieved.
+to only call {\tt opt} when an improvement can be achieved.
 
 \bigskip
 The designs in {\tt yosys-bigsim} are a good playground for experimenting with
@@ -268,7 +268,7 @@ memory -nomap; techmap -map my_memory_map.v; memory_map
 \end{frame}
 
 \begin{frame}[t, fragile]{\subsecname{} -- Example 1/2}
-\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -10cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
+\vbox to 0cm{\includegraphics[width=0.7\linewidth,trim=0cm 0cm 0cm -10cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
 \vskip-1cm
 \begin{columns}
 \column[t]{5cm}
@@ -320,7 +320,7 @@ fsm_map             # unless got option -nomap
 \end{frame}
 
 \begin{frame}{\subsecname{} -- details}
-Some details on the most importand commands from the {\tt fsm\_*} group:
+Some details on the most important commands from the {\tt fsm\_*} group:
 
 \bigskip
 The {\tt fsm\_detect} command identifies FSM state registers and marks them
@@ -367,7 +367,7 @@ to map all RTL cell types to a generic library of built-in logic gates and regis
 
 \bigskip
 \begin{block}{The built-in logic gate types are:}
-{\tt \$\_INV\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
+{\tt \$\_NOT\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
 \end{block}
 
 \bigskip
@@ -455,7 +455,7 @@ read_verilog -D WITH_MULT cpu_alu.v
 hierarchy -check -top cpu_top
 
 # high-level synthesis
-proc; opt; memory -nomap;; fsm; opt
+proc; opt; fsm;; memory -nomap; opt
 
 # substitute block rams
 techmap -map map_rams.v
@@ -497,7 +497,7 @@ the next part (Section 3, ``Advanced Synthesis'') of this presentation.}
 \item Yosys provides commands for each phase of the synthesis.
 \item Each command solves a (more or less) simple problem.
 \item Complex commands are often only front-ends to simple commands.
-\item {\tt proc; opt; memory; opt; fsm; opt; techmap; opt; abc;;}
+\item {\tt proc; opt; fsm; opt; memory; opt; techmap; opt; abc;;}
 \end{itemize}
 
 \bigskip