kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero

[yosys.git] / manual / PRESENTATION_Prog.tex

diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex
index 6b105a701777a88d74227b6ba71e178fcf082df2..b85eda89272b0cb1cbb3fd059c55fab22c0588cb 100644 (file)
--- a/manual/PRESENTATION_Prog.tex
+++ b/manual/PRESENTATION_Prog.tex
@@ -477,7 +477,7 @@ log("Name of this module: %s\n", log_id(module->name));
 \medskip
 Use {\tt log\_header()} and {\tt log\_push()}/{\tt log\_pop()} to structure log messages:
 \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-log_header("Doing important stuff!\n");
+log_header(design, "Doing important stuff!\n");
 log_push();
 for (int i = 0; i < 10; i++)
     log("Log message #%d.\n", i);
@@ -534,7 +534,7 @@ struct MyPass : public Pass {
         log("Modules in current design:\n");
         for (auto mod : design->modules())
             log("  %s (%d wires, %d cells)\n", log_id(mod),
-                    GetSize(mod->wires), GetSize(mod->cells));
+                    GetSize(mod->wires()), GetSize(mod->cells()));
     }
 } MyPass;
 \end{lstlisting}