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kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
[yosys.git]
/
manual
/
PRESENTATION_Prog.tex
diff --git
a/manual/PRESENTATION_Prog.tex
b/manual/PRESENTATION_Prog.tex
index 73c2bf4196443948d744fe24cdd707d7f6e0c0ac..b85eda89272b0cb1cbb3fd059c55fab22c0588cb 100644
(file)
--- a/
manual/PRESENTATION_Prog.tex
+++ b/
manual/PRESENTATION_Prog.tex
@@
-534,7
+534,7
@@
struct MyPass : public Pass {
log("Modules in current design:\n");
for (auto mod : design->modules())
log(" %s (%d wires, %d cells)\n", log_id(mod),
- GetSize(mod->wires
), GetSize(mod->cells
));
+ GetSize(mod->wires
()), GetSize(mod->cells()
));
}
} MyPass;
\end{lstlisting}