kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero

[yosys.git] / manual / PRESENTATION_Prog.tex

diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex
index 96189e55f3f8e3d0119470b042068567b0a750fc..b85eda89272b0cb1cbb3fd059c55fab22c0588cb 100644 (file)
--- a/manual/PRESENTATION_Prog.tex
+++ b/manual/PRESENTATION_Prog.tex
@@ -124,7 +124,7 @@ has been executed.
 
 \begin{frame}{\subsecname}
 The RTLIL data structures are simple structs utilizing {\tt pool<>} and
-{\tt dict<>} containers (drop-in replacementments for {\tt
+{\tt dict<>} containers (drop-in replacements for {\tt
 std::unordered\_set<>} and {\tt std::unordered\_map<>}).
 
 \bigskip
@@ -325,7 +325,7 @@ Simulation models (i.e. {\it documentation\/} :-) for the internal cell library:
 
 \bigskip
 The lower-case cell types (such as {\tt \$and}) are parameterized cells of variable
-width. This so-called {\it RTL Cells\/} are the cells described in {\tt simlib.v}. 
+width. This so-called {\it RTL Cells\/} are the cells described in {\tt simlib.v}.
 
 \bigskip
 The upper-case cell types (such as {\tt \$\_AND\_}) are single-bit cells that are not
@@ -413,7 +413,7 @@ When modifying existing modules, stick to the following DOs and DON'Ts:
 
 \item Use {\tt module->fixup\_ports()} after changing the {\tt port\_*} properties of wires.
 
-\item You can safely remove cells or change the {\tt connetions} property of a cell, but be careful when
+\item You can safely remove cells or change the {\tt connections} property of a cell, but be careful when
 changing the size of the {\tt SigSpec} connected to a cell port.
 
 \item Use the {\tt SigMap} helper class (see next slide) when you need a unique handle for each signal bit.
@@ -477,7 +477,7 @@ log("Name of this module: %s\n", log_id(module->name));
 \medskip
 Use {\tt log\_header()} and {\tt log\_push()}/{\tt log\_pop()} to structure log messages:
 \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
-log_header("Doing important stuff!\n");
+log_header(design, "Doing important stuff!\n");
 log_push();
 for (int i = 0; i < 10; i++)
     log("Log message #%d.\n", i);
@@ -534,7 +534,7 @@ struct MyPass : public Pass {
         log("Modules in current design:\n");
         for (auto mod : design->modules())
             log("  %s (%d wires, %d cells)\n", log_id(mod),
-                    GetSize(mod->wires), GetSize(mod->cells));
+                    GetSize(mod->wires()), GetSize(mod->cells()));
     }
 } MyPass;
 \end{lstlisting}