-\r
-@inproceedings{intersynth,\r
- title={Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic},\r
- author={Clifford Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm},\r
- booktitle={FDL Proceeding of the 2012 Forum on Specification and Design Languages},\r
- pages={194--201},\r
- year={2012}\r
-}\r
-\r
-@incollection{intersynthFdlBookChapter,\r
- title={Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures},\r
- author={Johann Glaser and Clifford Wolf},\r
- booktitle={Advances in Models, Methods, and Tools for Complex Chip Design --- Selected contributions from FDL'12},\r
- editor={Jan Haase},\r
- publisher={Springer},\r
- year={2013},\r
- note={to appear}\r
-}\r
-\r
-@unpublished{BACC,\r
- author = {Clifford Wolf},\r
- title = {Design and Implementation of the Yosys Open SYnthesis Suite},\r
- note = {Bachelor Thesis, Vienna University of Technology},\r
- year = {2013}\r
-}\r
-\r
-@unpublished{VerilogFossEval,\r
- author = {Clifford Wolf},\r
- title = {Evaluation of Open Source Verilog Synthesis Tools for Feature-Completeness and Extensibility},\r
- note = {Unpublished Student Research Paper, Vienna University of Technology},\r
- year = {2012}\r
-}\r
-\r
-@article{ABEL,\r
- title={A High-Level Design Language for Programmable Logic Devices},\r
- author={Kyu Y. Lee and Michael Holley and Mary Bailey and Walter Bright},\r
- journal={VLSI Design (Manhasset NY: CPM Publications)},\r
- year={June 1985},\r
- pages={50-62}\r
-}\r
-\r
-@MISC{Cheng93vl2mv:a,\r
- author = {S-T Cheng and G York and R K Brayton},\r
- title = {VL2MV: A Compiler from Verilog to BLIF-MV},\r
- year = {1993}\r
-}\r
-\r
-@MISC{Odin,\r
- author = {Peter Jamieson and Jonathan Rose},\r
- title = {A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS},\r
- year = {2005}\r
-}\r
-\r
-@inproceedings{vtr2012,\r
- title={The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing},\r
- author={Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},\r
- booktitle={Proceedings of the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},\r
- pages={77--86},\r
- year={2012},\r
- organization={ACM}\r
-}\r
-\r
-@MISC{LogicSynthesis,\r
- author = {G D Hachtel and F Somenzi},\r
- title = {Logic Synthesis and Verification Algorithms},\r
- year = {1996}\r
-}\r
-\r
-@ARTICLE{Verilog2005, \r
- journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)},\r
- title={IEEE Standard for Verilog Hardware Description Language}, \r
- year={2006}, \r
- doi={10.1109/IEEESTD.2006.99495}\r
-}\r
-\r
-@ARTICLE{VerilogSynth, \r
- journal={IEEE Std 1364.1-2002},\r
- title={IEEE Standard for Verilog Register Transfer Level Synthesis}, \r
- year={2002}, \r
- doi={10.1109/IEEESTD.2002.94220}\r
-}\r
-\r
-@ARTICLE{VHDL,\r
- journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, title={IEEE Standard VHDL Language Reference Manual},\r
- year={2009},\r
- month={26},\r
- doi={10.1109/IEEESTD.2009.4772740}\r
-}\r
-\r
-@ARTICLE{VHDLSynth,\r
- journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis},\r
- year={2004},\r
- doi={10.1109/IEEESTD.2004.94802}\r
-}\r
-\r
-@ARTICLE{IP-XACT, \r
-journal={IEEE Std 1685-2009}, title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows}, \r
-year={2010}, \r
-pages={C1-360}, \r
-keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema}, \r
-doi={10.1109/IEEESTD.2010.5417309},}\r
-\r
-@book{Dragonbook,\r
-author = {Aho, Alfred V. and Sethi, Ravi and Ullman, Jeffrey D.},\r
-title = {Compilers: principles, techniques, and tools},\r
-year = {1986},\r
-isbn = {0-201-10088-6},\r
-publisher = {Addison-Wesley Longman Publishing Co., Inc.},\r
-address = {Boston, MA, USA},\r
-} \r
-\r
-@INPROCEEDINGS{Cummings00,\r
-author = {Clifford E. Cummings and Sunburst Design Inc},\r
-title = {Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill},\r
-booktitle = {SNUG (Synopsys Users Group) 2000 User Papers, section-MC1 (1 st paper},\r
-year = {2000}\r
-}\r
-\r
-@ARTICLE{MURPHY,\r
- author={D. L. Klipstein},\r
- journal={Cahners Publishing Co., EEE Magazine, Vol. 15, No. 8},\r
- title={The Contributions of Edsel Murphy to the Understanding of the Behavior of Inanimate Objects},\r
- year={August 1967}\r
-}\r
-\r
-@INPROCEEDINGS{fsmextract, \r
-author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren}, \r
-booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on}, \r
-title={A highly efficient method for extracting FSMs from flattened gate-level netlist}, \r
-year={2010}, \r
-pages={2610-2613}, \r
-keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, \r
-doi={10.1109/ISCAS.2010.5537093},}\r
-\r
-@ARTICLE{MultiLevelLogicSynth, \r
-author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.}, \r
-journal={Proceedings of the IEEE}, \r
-title={Multilevel logic synthesis}, \r
-year={1990}, \r
-volume={78}, \r
-number={2}, \r
-pages={264-300}, \r
-keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon}, \r
-doi={10.1109/5.52213}, \r
-ISSN={0018-9219},}\r
-\r
-@article{UllmannSubgraphIsomorphism,\r
- author = {Ullmann, J. R.},\r
- title = {An Algorithm for Subgraph Isomorphism},\r
- journal = {J. ACM},\r
- issue_date = {Jan. 1976},\r
- volume = {23},\r
- number = {1},\r
- month = jan,\r
- year = {1976},\r
- issn = {0004-5411},\r
- pages = {31--42},\r
- numpages = {12},\r
- doi = {10.1145/321921.321925},\r
- acmid = {321925},\r
- publisher = {ACM},\r
- address = {New York, NY, USA},\r
-} \r
+
+@inproceedings{intersynth,
+ title={Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic},
+ author={Clifford Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm},
+ booktitle={FDL Proceeding of the 2012 Forum on Specification and Design Languages},
+ pages={194--201},
+ year={2012}
+}
+
+@incollection{intersynthFdlBookChapter,
+ title={Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures},
+ author={Johann Glaser and Clifford Wolf},
+ booktitle={Advances in Models, Methods, and Tools for Complex Chip Design --- Selected contributions from FDL'12},
+ editor={Jan Haase},
+ publisher={Springer},
+ year={2013},
+ note={to appear}
+}
+
+@unpublished{BACC,
+ author = {Clifford Wolf},
+ title = {Design and Implementation of the Yosys Open SYnthesis Suite},
+ note = {Bachelor Thesis, Vienna University of Technology},
+ year = {2013}
+}
+
+@unpublished{VerilogFossEval,
+ author = {Clifford Wolf},
+ title = {Evaluation of Open Source Verilog Synthesis Tools for Feature-Completeness and Extensibility},
+ note = {Unpublished Student Research Paper, Vienna University of Technology},
+ year = {2012}
+}
+
+@article{ABEL,
+ title={A High-Level Design Language for Programmable Logic Devices},
+ author={Kyu Y. Lee and Michael Holley and Mary Bailey and Walter Bright},
+ journal={VLSI Design (Manhasset NY: CPM Publications)},
+ year={June 1985},
+ pages={50-62}
+}
+
+@MISC{Cheng93vl2mv:a,
+ author = {S-T Cheng and G York and R K Brayton},
+ title = {VL2MV: A Compiler from Verilog to BLIF-MV},
+ year = {1993}
+}
+
+@MISC{Odin,
+ author = {Peter Jamieson and Jonathan Rose},
+ title = {A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS},
+ year = {2005}
+}
+
+@inproceedings{vtr2012,
+ title={The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing},
+ author={Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},
+ booktitle={Proceedings of the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
+ pages={77--86},
+ year={2012},
+ organization={ACM}
+}
+
+@MISC{LogicSynthesis,
+ author = {G D Hachtel and F Somenzi},
+ title = {Logic Synthesis and Verification Algorithms},
+ year = {1996}
+}
+
+@ARTICLE{Verilog2005,
+ journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)},
+ title={IEEE Standard for Verilog Hardware Description Language},
+ year={2006},
+ doi={10.1109/IEEESTD.2006.99495}
+}
+
+@ARTICLE{VerilogSynth,
+ journal={IEEE Std 1364.1-2002},
+ title={IEEE Standard for Verilog Register Transfer Level Synthesis},
+ year={2002},
+ doi={10.1109/IEEESTD.2002.94220}
+}
+
+@ARTICLE{VHDL,
+ journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, title={IEEE Standard VHDL Language Reference Manual},
+ year={2009},
+ month={26},
+ doi={10.1109/IEEESTD.2009.4772740}
+}
+
+@ARTICLE{VHDLSynth,
+ journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis},
+ year={2004},
+ doi={10.1109/IEEESTD.2004.94802}
+}
+
+@ARTICLE{IP-XACT,
+journal={IEEE Std 1685-2009}, title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows},
+year={2010},
+pages={C1-360},
+keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema},
+doi={10.1109/IEEESTD.2010.5417309},}
+
+@book{Dragonbook,
+author = {Aho, Alfred V. and Sethi, Ravi and Ullman, Jeffrey D.},
+title = {Compilers: principles, techniques, and tools},
+year = {1986},
+isbn = {0-201-10088-6},
+publisher = {Addison-Wesley Longman Publishing Co., Inc.},
+address = {Boston, MA, USA},
+}
+
+@INPROCEEDINGS{Cummings00,
+author = {Clifford E. Cummings and Sunburst Design Inc},
+title = {Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill},
+booktitle = {SNUG (Synopsys Users Group) 2000 User Papers, section-MC1 (1 st paper},
+year = {2000}
+}
+
+@ARTICLE{MURPHY,
+ author={D. L. Klipstein},
+ journal={Cahners Publishing Co., EEE Magazine, Vol. 15, No. 8},
+ title={The Contributions of Edsel Murphy to the Understanding of the Behavior of Inanimate Objects},
+ year={August 1967}
+}
+
+@INPROCEEDINGS{fsmextract,
+author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren},
+booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on},
+title={A highly efficient method for extracting FSMs from flattened gate-level netlist},
+year={2010},
+pages={2610-2613},
+keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing},
+doi={10.1109/ISCAS.2010.5537093},}
+
+@ARTICLE{MultiLevelLogicSynth,
+author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.},
+journal={Proceedings of the IEEE},
+title={Multilevel logic synthesis},
+year={1990},
+volume={78},
+number={2},
+pages={264-300},
+keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon},
+doi={10.1109/5.52213},
+ISSN={0018-9219},}
+
+@article{UllmannSubgraphIsomorphism,
+ author = {Ullmann, J. R.},
+ title = {An Algorithm for Subgraph Isomorphism},
+ journal = {J. ACM},
+ issue_date = {Jan. 1976},
+ volume = {23},
+ number = {1},
+ month = jan,
+ year = {1976},
+ issn = {0004-5411},
+ pages = {31--42},
+ numpages = {12},
+ doi = {10.1145/321921.321925},
+ acmid = {321925},
+ publisher = {ACM},
+ address = {New York, NY, USA},
+}
projects / yosys.git / blobdiff