-\r
-@misc{YosysGit,\r
- author = {Clifford Wolf},\r
- title = {{Yosys Open SYnthesis Suite (YOSYS)}},\r
- note = {\url{http://github.com/cliffordwolf/yosys}}\r
-}\r
-\r
-@misc{YosysTestsGit,\r
- author = {Clifford Wolf},\r
- title = {{Yosys Test Bench}},\r
- note = {\url{http://github.com/cliffordwolf/yosys-tests}}\r
-}\r
-\r
-@misc{VlogHammer,\r
- author = {Clifford Wolf},\r
- title = {{VlogHammer Verilog Synthesis Regression Tests}},\r
- note = {\url{http://github.com/cliffordwolf/VlogHammer}}\r
-}\r
-\r
-@misc{Icarus,\r
- author = {Stephen Williams},\r
- title = {{Icarus Verilog}},\r
- note = {Version 0.8.7, \url{http://iverilog.icarus.com/}}\r
-}\r
-\r
-@misc{VTR,\r
- author= {Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},\r
- title = {{The Verilog-to-Routing (VTR) Project for FPGAs}},\r
- note = {Version 1.0, \url{https://code.google.com/p/vtr-verilog-to-routing/}}\r
-}\r
-\r
-@misc{HANA,\r
- author = {Parvez Ahmad},\r
- title = {{HDL Analyzer and Netlist Architect (HANA)}},\r
- note = {Verison linux64-1.0-alpha (2012-10-14), \url{http://sourceforge.net/projects/sim-sim/}}\r
-}\r
-\r
-@misc{MVSIS,\r
- author = {MVSIS group at Berkeley studies logic synthesis and verification for VLSI design},\r
- title = {{MVSIS: Logic Synthesis and Verification}},\r
- note = {Version 3.0, \url{http://embedded.eecs.berkeley.edu/mvsis/}}\r
-}\r
-\r
-@misc{VIS,\r
- author = {{The VIS group}},\r
- title = {{VIS: A system for Verification and Synthesis}},\r
- note = {Version 2.4, \url{http://vlsi.colorado.edu/~vis/}}\r
-}\r
-\r
-@misc{ABC,\r
- author = {{Berkeley Logic Synthesis and Verification Group}},\r
- title = {{ABC: A System for Sequential Synthesis and Verification}},\r
- note = {HQ Rev b5750272659f, 2012-10-28, \url{http://www.eecs.berkeley.edu/~alanmi/abc/}}\r
-}\r
-\r
-@misc{AIGER,\r
- author = {{Armin Biere, Johannes Kepler University Linz, Austria}},\r
- title = {{AIGER}},\r
- note = {\url{http://fmv.jku.at/aiger/}}\r
-}\r
-\r
-@misc{XilinxWebPACK,\r
- author = {{Xilinx, Inc.}},\r
- title = {{ISE WebPACK Design Software}},\r
- note = {\url{http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm}}\r
-}\r
-\r
-@misc{QuartusWeb,\r
- author = {{Altera, Inc.}},\r
- title = {{Quartus II Web Edition Software}},\r
- note = {\url{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}}\r
-}\r
-\r
-@misc{OR1200,\r
- title = {{OpenRISC 1200 CPU}},\r
- note = {\url{http://opencores.org/or1k/OR1200\_OpenRISC\_Processor}}\r
-}\r
-\r
-@misc{openMSP430,\r
- title = {{openMSP430 CPU}},\r
- note = {\url{http://opencores.org/project,openmsp430}}\r
-}\r
-\r
-@misc{i2cmaster,\r
- title = {{OpenCores I$^2$C Core}},\r
- note = {\url{http://opencores.org/project,i2c}}\r
-}\r
-\r
-@misc{k68,\r
- title = {{OpenCores k68 Core}},\r
- note = {\url{http://opencores.org/project,k68}}\r
-}\r
-\r
-@misc{bison,\r
- title = {{GNU Bison}},\r
- note = {\url{http://www.gnu.org/software/bison/}}\r
-}\r
-\r
-@misc{flex,\r
- title = {{Flex}},\r
- note = {\url{http://flex.sourceforge.net/}}\r
-}\r
-\r
-@misc{C_to_Verilog,\r
- title = {{C-to-Verilog}},\r
- note = {\url{http://www.c-to-verilog.com/}}\r
-}\r
-\r
-@misc{LegUp,\r
- title = {{LegUp}},\r
- note = {\url{http://legup.eecg.utoronto.ca/}}\r
-}\r
-\r
-@misc{LibertyFormat,\r
- title = {{The Liberty Library Modeling Standard}},\r
- note = {\url{http://www.opensourceliberty.org/}}\r
-}\r
-\r
-@misc{ASIC-WORLD,\r
- title = {{World of ASIC}},\r
- note = {\url{http://www.asic-world.com/}}\r
-}\r
-\r
-@misc{Formality,\r
- title = {{Synopsys Formality Equivalence Checking}},\r
- note = {\url{http://www.synopsys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx}},\r
-}\r
-\r
-@misc{bigint,\r
- author = {Matt McCutchen},\r
- title = {{C++ Big Integer Library}},\r
- note = {\url{http://mattmccutchen.net/bigint/}}\r
-}\r
-\r
-@misc{smallsha1,\r
- author = {Micael Hildenborg},\r
- title = {{smallsha1}},\r
- note = {\url{https://code.google.com/p/smallsha1/}}\r
-}\r
-\r
+
+@misc{YosysGit,
+ author = {Clifford Wolf},
+ title = {{Yosys Open SYnthesis Suite (YOSYS)}},
+ note = {\url{http://github.com/cliffordwolf/yosys}}
+}
+
+@misc{YosysTestsGit,
+ author = {Clifford Wolf},
+ title = {{Yosys Test Bench}},
+ note = {\url{http://github.com/cliffordwolf/yosys-tests}}
+}
+
+@misc{VlogHammer,
+ author = {Clifford Wolf},
+ title = {{VlogHammer Verilog Synthesis Regression Tests}},
+ note = {\url{http://github.com/cliffordwolf/VlogHammer}}
+}
+
+@misc{Icarus,
+ author = {Stephen Williams},
+ title = {{Icarus Verilog}},
+ note = {Version 0.8.7, \url{http://iverilog.icarus.com/}}
+}
+
+@misc{VTR,
+ author= {Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},
+ title = {{The Verilog-to-Routing (VTR) Project for FPGAs}},
+ note = {Version 1.0, \url{https://code.google.com/p/vtr-verilog-to-routing/}}
+}
+
+@misc{HANA,
+ author = {Parvez Ahmad},
+ title = {{HDL Analyzer and Netlist Architect (HANA)}},
+ note = {Verison linux64-1.0-alpha (2012-10-14), \url{http://sourceforge.net/projects/sim-sim/}}
+}
+
+@misc{MVSIS,
+ author = {MVSIS group at Berkeley studies logic synthesis and verification for VLSI design},
+ title = {{MVSIS: Logic Synthesis and Verification}},
+ note = {Version 3.0, \url{http://embedded.eecs.berkeley.edu/mvsis/}}
+}
+
+@misc{VIS,
+ author = {{The VIS group}},
+ title = {{VIS: A system for Verification and Synthesis}},
+ note = {Version 2.4, \url{http://vlsi.colorado.edu/~vis/}}
+}
+
+@misc{ABC,
+ author = {{Berkeley Logic Synthesis and Verification Group}},
+ title = {{ABC: A System for Sequential Synthesis and Verification}},
+ note = {HQ Rev b5750272659f, 2012-10-28, \url{http://www.eecs.berkeley.edu/~alanmi/abc/}}
+}
+
+@misc{AIGER,
+ author = {{Armin Biere, Johannes Kepler University Linz, Austria}},
+ title = {{AIGER}},
+ note = {\url{http://fmv.jku.at/aiger/}}
+}
+
+@misc{XilinxWebPACK,
+ author = {{Xilinx, Inc.}},
+ title = {{ISE WebPACK Design Software}},
+ note = {\url{http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm}}
+}
+
+@misc{QuartusWeb,
+ author = {{Altera, Inc.}},
+ title = {{Quartus II Web Edition Software}},
+ note = {\url{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}}
+}
+
+@misc{OR1200,
+ title = {{OpenRISC 1200 CPU}},
+ note = {\url{http://opencores.org/or1k/OR1200\_OpenRISC\_Processor}}
+}
+
+@misc{openMSP430,
+ title = {{openMSP430 CPU}},
+ note = {\url{http://opencores.org/project,openmsp430}}
+}
+
+@misc{i2cmaster,
+ title = {{OpenCores I$^2$C Core}},
+ note = {\url{http://opencores.org/project,i2c}}
+}
+
+@misc{k68,
+ title = {{OpenCores k68 Core}},
+ note = {\url{http://opencores.org/project,k68}}
+}
+
+@misc{bison,
+ title = {{GNU Bison}},
+ note = {\url{http://www.gnu.org/software/bison/}}
+}
+
+@misc{flex,
+ title = {{Flex}},
+ note = {\url{http://flex.sourceforge.net/}}
+}
+
+@misc{C_to_Verilog,
+ title = {{C-to-Verilog}},
+ note = {\url{http://www.c-to-verilog.com/}}
+}
+
+@misc{LegUp,
+ title = {{LegUp}},
+ note = {\url{http://legup.eecg.utoronto.ca/}}
+}
+
+@misc{LibertyFormat,
+ title = {{The Liberty Library Modeling Standard}},
+ note = {\url{http://www.opensourceliberty.org/}}
+}
+
+@misc{ASIC-WORLD,
+ title = {{World of ASIC}},
+ note = {\url{http://www.asic-world.com/}}
+}
+
+@misc{Formality,
+ title = {{Synopsys Formality Equivalence Checking}},
+ note = {\url{http://www.synopsys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx}},
+}
+
+@misc{bigint,
+ author = {Matt McCutchen},
+ title = {{C++ Big Integer Library}},
+ note = {\url{http://mattmccutchen.net/bigint/}}
+}
+
projects / yosys.git / blobdiff