Bug 1244: changes to images

[libreriscv.git] / meetings / dmitry_2023-11-24.mdwn

diff --git a/meetings/dmitry_2023-11-24.mdwn b/meetings/dmitry_2023-11-24.mdwn
index 97e72d4241f53ada2475f2bed5275afc60a3c78d..55954356c20d1308dba6d87877ea9669ab1324c7 100644 (file)
--- a/meetings/dmitry_2023-11-24.mdwn
+++ b/meetings/dmitry_2023-11-24.mdwn
@@ -1,7 +1,8 @@
 # Friday 24th November 17:00 UTC
 
 - A meeting with Dmitry, David, James, Luke, and Andrey to explain the
-new grants for extending SV for RISC-V.
+new grants for updating Simple-V for RISC-V (first implemented 4 years
+ago, now in need of an update)
 
 Main points to take away:
 
@@ -25,32 +26,34 @@ full feature set of SimpleV. Link to LibreSOC'
 
 ## New Binutils Grant
 
-- [[nlnet_2023_svp64_riscv_binutils]]
+- [[nlnet_2023_simplev_riscv_binutils]]
 
 - Primarily Dmitry doing most of the work.
+- Communication on Simple-V formats to be defined by luke and jacob
 
 ## Primary Tasks
 
   1. Finish writing libopid, some of the work started 4 months ago
-(no RfPs will be submitted for that work). Link to
+(no RfPs can be submitted for that work). Link to
 [repo](https://git.libre-soc.org/?p=mdis.git;a=summary)
-  2. Convert existing PowerISA (SFFS) `isndb` instruction database to libopid.
+  2. Convert existing PowerISA (SFFS) `isndb` instruction database to libopid
+   (without losing CSV files which are machine-readable by other projects)
   3. Create RISC-V instruction database using libopid.
   4. Implement SVP64 PowerISA in libopid.
-  5. Implement SV for RISC-V in libopid.
+  5. Implement SimpleV for RISC-V in libopid.
      - SVP32 (16+16) - 16-bit prefix for 16-bit compressed instructions.
      - SVP48 (16+32) - 16-bit prefix for 32-bit instructions.
      - SVP64 (32+32) - 32-bit prefix for 64-bit instructions.
 
-The 16-bit prefix saves instruction space in memory
-(but with limited feature set).
-
-The 32-bit prefix gives full access to SimpleV feature set
-(128 reg's, all SV modes such as data dependent fail-first, etc.)
+* The 16-bit prefix saves instruction space in memory
+ (but with limited feature set: 128 regs span but cruder spacing).
+* The 32-bit prefix gives full access to SimpleV feature set
+ (128 regs, all SV modes such as data dependent fail-first, etc.)
 
 # Defining SVPxxSingle
 
 Another point mentioned after Dmitry left is the need to define SVPxxSingle.
+[[openpower/sv/svp64-single]]
 
 For both RISC-V and PowerISA need to define:
 
@@ -59,7 +62,7 @@ For both RISC-V and PowerISA need to define:
 - SVP64Single
 
 *(Andrey: Why do these need to be defined for PowerISA?
-To also save on instruction memory?)*
+A: see page and bugreport. full 128 reg access)*
 
 Doing this work for both ISAs at the same time isn't too difficult,
 as the SVPxxSingle format will be the same for both ISAs.