syscon: Add syscon registers

[microwatt.git] / microwatt.core

diff --git a/microwatt.core b/microwatt.core
index ee48376d52bd4dc056d433c266a4f4a472604f7f..a1ae14bc82f5ae0a6abf1667358ff97b4fa10479 100644 (file)
--- a/microwatt.core
+++ b/microwatt.core
@@ -45,6 +45,8 @@ filesets:
       - wishbone_debug_master.vhdl
       - wishbone_bram_wrapper.vhdl
       - soc.vhdl
+      - xics.vhdl
+      - syscon.vhdl
     file_type : vhdlSource-2008
 
   fpga:
@@ -54,7 +56,6 @@ filesets:
       - fpga/pp_fifo.vhd
       - fpga/pp_soc_uart.vhd
       - fpga/pp_utilities.vhd
-      - fpga/toplevel.vhdl
       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
     file_type : vhdlSource-2008
 
@@ -70,21 +71,28 @@ filesets:
     files:
       - fpga/nexys_a7.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
 
   nexys_video:
     files:
       - fpga/nexys-video.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
 
   arty_a7:
     files:
       - fpga/arty_a7.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
 
   cmod_a7-35:
     files:
       - fpga/cmod_a7-35.xdc : {file_type : xdc}
       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
+
+  litedram:
+      depend : [":microwatt:litedram"]
 
 targets:
   nexys_a7:
@@ -100,7 +108,7 @@ targets:
       vivado: {part : xc7a100tcsg324-1}
     toplevel : toplevel
 
-  nexys_video:
+  nexys_video-nodram:
     default_tool: vivado
     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
     parameters :
@@ -113,7 +121,20 @@ targets:
       vivado: {part : xc7a200tsbg484-1}
     toplevel : toplevel
 
-  arty_a7-35:
+  nexys_video:
+    default_tool: vivado
+    filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram]
+    parameters:
+      - memory_size
+      - ram_init_file
+      - use_litedram=true
+      - disable_flatten_core
+    generate: [dram_nexys_video]
+    tools:
+      vivado: {part : xc7a200tsbg484-1}
+    toplevel : toplevel
+
+  arty_a7-35-nodram:
     default_tool: vivado
     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
     parameters :
@@ -126,7 +147,20 @@ targets:
       vivado: {part : xc7a35ticsg324-1L}
     toplevel : toplevel
 
-  arty_a7-100:
+  arty_a7-35:
+    default_tool: vivado
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
+    parameters :
+      - memory_size
+      - ram_init_file
+      - use_litedram=true
+      - disable_flatten_core
+    generate: [dram_arty]
+    tools:
+      vivado: {part : xc7a35ticsg324-1L}
+    toplevel : toplevel
+
+  arty_a7-100-nodram:
     default_tool: vivado
     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
     parameters :
@@ -139,6 +173,19 @@ targets:
       vivado: {part : xc7a100ticsg324-1L}
     toplevel : toplevel
 
+  arty_a7-100:
+    default_tool: vivado
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
+    parameters:
+      - memory_size
+      - ram_init_file
+      - use_litedram=true
+      - disable_flatten_core
+    generate: [dram_arty]
+    tools:
+      vivado: {part : xc7a100ticsg324-1L}
+    toplevel : toplevel
+
   cmod_a7-35:
     default_tool: vivado
     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
@@ -159,11 +206,21 @@ targets:
       vivado: {pnr : none}
     toplevel: core
 
+generate:
+  dram_arty:
+    generator: litedram_gen
+    parameters: {board : arty}
+
+  dram_nexys_video:
+    generator: litedram_gen
+    parameters: {board : nexys-video}
+
 parameters:
   memory_size:
     datatype    : int
     description : On-chip memory size (bytes)
     paramtype   : generic
+    default     : 16384
 
   ram_init_file:
     datatype    : file
@@ -185,10 +242,16 @@ parameters:
     datatype    : int
     description : Generated system clock frequency in HZ (for top-generic based boards)
     paramtype   : generic
-    default     : 50000000
+    default     : 100000000
 
   disable_flatten_core:
     datatype    : bool
     description : Prevent Vivado from flattening the main core components
     paramtype   : generic
     default     : false
+
+  use_litedram:
+    datatype    : bool
+    description : Use liteDRAM
+    paramtype   : generic
+    default     : false