Reformat execute2

[microwatt.git] / microwatt.core

diff --git a/microwatt.core b/microwatt.core
index b82b0d02125289f1fd92726500d004ed90c7a3b7..b62aef9495a9e03c6a67cab5adad91193245c504 100644 (file)
--- a/microwatt.core
+++ b/microwatt.core
@@ -24,19 +24,25 @@ filesets:
       - loadstore2.vhdl
       - multiply.vhdl
       - writeback.vhdl
-      - wishbone_arbiter.vhdl
       - insn_helpers.vhdl
       - core.vhdl
+      - icache.vhdl
     file_type : vhdlSource-2008
 
   soc:
+    files:
+      - wishbone_arbiter.vhdl
+      - soc.vhdl
+    file_type : vhdlSource-2008
+
+  fpga:
     files:
       - fpga/pp_fifo.vhd
-      - fpga/pp_soc_memory.vhd
+      - fpga/mw_soc_memory.vhdl
       - fpga/soc_reset.vhdl
       - fpga/pp_soc_uart.vhd
       - fpga/pp_utilities.vhd
-      - fpga/toplevel.vhd
+      - fpga/toplevel.vhdl
       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
     file_type : vhdlSource-2008
 
@@ -55,11 +61,15 @@ filesets:
       - fpga/arty_a7-35.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 
+  cmod_a7-35:
+    files:
+      - fpga/cmod_a7-35.xdc : {file_type : xdc}
+      - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
 
 targets:
   nexys_a7:
     default_tool: vivado
-    filesets: [core, nexys_a7, soc]
+    filesets: [core, nexys_a7, soc, fpga]
     parameters : [memory_size, ram_init_file]
     tools:
       vivado: {part : xc7a100tcsg324-1}
@@ -67,7 +77,7 @@ targets:
 
   nexys_video:
     default_tool: vivado
-    filesets: [core, nexys_video, soc]
+    filesets: [core, nexys_video, soc, fpga]
     parameters : [memory_size, ram_init_file]
     tools:
       vivado: {part : xc7a200tsbg484-1}
@@ -75,14 +85,22 @@ targets:
 
   arty_a7-35:
     default_tool: vivado
-    filesets: [core, arty_a7-35, soc]
+    filesets: [core, arty_a7-35, soc, fpga]
     parameters : [memory_size, ram_init_file]
     tools:
       vivado: {part : xc7a35ticsg324-1L}
     toplevel : toplevel
 
+  cmod_a7-35:
+    default_tool: vivado
+    filesets: [core, cmod_a7-35, soc, fpga]
+    parameters : [memory_size, ram_init_file, reset_low=false]
+    tools:
+      vivado: {part : xc7a35tcpg236-1}
+    toplevel : toplevel
+
   synth:
-    filesets: [core]
+    filesets: [core, soc]
     tools:
       vivado: {pnr : none}
     toplevel: core
@@ -97,3 +115,8 @@ parameters:
     datatype    : file
     description : Initial on-chip RAM contents
     paramtype   : generic
+
+  reset_low:
+    datatype    : bool
+    description : External reset button polarity
+    paramtype   : generic