fpga: Arty A7's don't need multiple filesets

[microwatt.git] / microwatt.core

diff --git a/microwatt.core b/microwatt.core
index 9604cee9d4069b789d15a6ec6c994d1dba3e3fef..f815c1509de8ac3083ec119661a8498ba640b941 100644 (file)
--- a/microwatt.core
+++ b/microwatt.core
@@ -68,14 +68,9 @@ filesets:
       - fpga/nexys-video.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 
-  arty_a7-35:
-    files:
-      - fpga/arty_a7-35.xdc : {file_type : xdc}
-      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
-
-  arty_a7-100:
+  arty_a7:
     files:
-      - fpga/arty_a7-35.xdc : {file_type : xdc}
+      - fpga/arty_a7.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 
   cmod_a7-35:
@@ -102,7 +97,7 @@ targets:
 
   arty_a7-35:
     default_tool: vivado
-    filesets: [core, arty_a7-35, soc, fpga, debug_xilinx]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx]
     parameters : [memory_size, ram_init_file]
     tools:
       vivado: {part : xc7a35ticsg324-1L}
@@ -110,7 +105,7 @@ targets:
 
   arty_a7-100:
     default_tool: vivado
-    filesets: [core, arty_a7-100, soc, fpga, debug_xilinx]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx]
     parameters : [memory_size, ram_init_file]
     tools:
       vivado: {part : xc7a100ticsg324-1L}