fpga: Arty A7's don't need multiple filesets

[microwatt.git] / microwatt.core

diff --git a/microwatt.core b/microwatt.core
index c77aceee3419f6db1158517795da1cdf92ac0919..f815c1509de8ac3083ec119661a8498ba640b941 100644 (file)
--- a/microwatt.core
+++ b/microwatt.core
@@ -23,23 +23,41 @@ filesets:
       - loadstore1.vhdl
       - loadstore2.vhdl
       - multiply.vhdl
+      - divider.vhdl
       - writeback.vhdl
-      - wishbone_arbiter.vhdl
       - insn_helpers.vhdl
+      - wishbone_debug_master.vhdl
       - core.vhdl
+      - icache.vhdl
+      - core_debug.vhdl
     file_type : vhdlSource-2008
 
   soc:
+    files:
+      - wishbone_arbiter.vhdl
+      - wishbone_debug_master.vhdl
+      - soc.vhdl
+    file_type : vhdlSource-2008
+
+  fpga:
     files:
       - fpga/pp_fifo.vhd
-      - fpga/pp_soc_memory.vhd
+      - fpga/mw_soc_memory.vhdl
       - fpga/soc_reset.vhdl
       - fpga/pp_soc_uart.vhd
       - fpga/pp_utilities.vhd
-      - fpga/toplevel.vhd
+      - fpga/toplevel.vhdl
       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
     file_type : vhdlSource-2008
 
+  debug_xilinx:
+    files:
+      - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
+
+  debug_dummy:
+    files:
+      - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
+
   nexys_a7:
     files:
       - fpga/nexys_a7.xdc : {file_type : xdc}
@@ -50,9 +68,9 @@ filesets:
       - fpga/nexys-video.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 
-  arty_a7-35:
+  arty_a7:
     files:
-      - fpga/arty_a7-35.xdc : {file_type : xdc}
+      - fpga/arty_a7.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 
   cmod_a7-35:
@@ -63,7 +81,7 @@ filesets:
 targets:
   nexys_a7:
     default_tool: vivado
-    filesets: [core, nexys_a7, soc]
+    filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
     parameters : [memory_size, ram_init_file]
     tools:
       vivado: {part : xc7a100tcsg324-1}
@@ -71,7 +89,7 @@ targets:
 
   nexys_video:
     default_tool: vivado
-    filesets: [core, nexys_video, soc]
+    filesets: [core, nexys_video, soc, fpga, debug_xilinx]
     parameters : [memory_size, ram_init_file]
     tools:
       vivado: {part : xc7a200tsbg484-1}
@@ -79,22 +97,30 @@ targets:
 
   arty_a7-35:
     default_tool: vivado
-    filesets: [core, arty_a7-35, soc]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx]
     parameters : [memory_size, ram_init_file]
     tools:
       vivado: {part : xc7a35ticsg324-1L}
     toplevel : toplevel
 
+  arty_a7-100:
+    default_tool: vivado
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx]
+    parameters : [memory_size, ram_init_file]
+    tools:
+      vivado: {part : xc7a100ticsg324-1L}
+    toplevel : toplevel
+
   cmod_a7-35:
     default_tool: vivado
-    filesets: [core, cmod_a7-35, soc]
+    filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
     parameters : [memory_size, ram_init_file, reset_low=false]
     tools:
       vivado: {part : xc7a35tcpg236-1}
     toplevel : toplevel
 
   synth:
-    filesets: [core]
+    filesets: [core, soc]
     tools:
       vivado: {pnr : none}
     toplevel: core