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[libreriscv.git] / mnolan.mdwn

diff --git a/mnolan.mdwn b/mnolan.mdwn
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+++ b/mnolan.mdwn
@@ -2,35 +2,87 @@
 
 Bored college student and contributor to Libre-SOC
 
+* [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=mtnolan&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
+
 # Status Tracking
 
 ## Currently working on
 
-
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
+    - with [[lkcl]]
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
+    - functions needed for simulator
+    - Shared 90% with [[lkcl]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=211> parent #198
+    - Formal proof of decoder
+    - EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=306> parent #195
+    - POWER9 ALU proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=332> parent #195
+    - POWER9 CR proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=335> parent #195
+    - POWER9 BRANCH proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=331> parent #195
+    - POWER9 LOGICAL proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=340> parent #195
+    - POWER9 ROTATE proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
+    - MultiCompUnit (and Function Units) proof
 
 ## Completed not yet submitted
 
- - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 
+## Submitted for RFP, waiting for payment
+
+
+## Paid
+
+### 2019-02-012 28-apr-2020 - Paid 08may2020
+
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=189> parent #48
+   - Add partitioned right shift to partitioned shifter
+   - EUR 150
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
    - Partitioned equals and greater than comparison
    - Shared 50% with [[lkcl]] 
-   - EUR 200
- - <http://bugs.libre-riscv.org/show_bug.cgi?id=172> 
+   - EUR 200 (each)
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=172> parent #48
    - Partitioned adc/sub/neg
    - EUR 150
- - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> 
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
    - partitioned scalar/vector shift
    - Shared 50% with [[lkcl]]
-   - EUR 350
+   - EUR 350 (each)
 
-## Submitted for RFP
+### 2019-10P-046 28-apr-2020 - Paid 08may2020 
 
-### Project 2019-02-012 Date 09feb2020
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
+    - auto-parser of POWER9
+    - Shared 50% with [[lkcl]]
+    - EUR 500 (each)
 
- - http://bugs.libre-riscv.org/show_bug.cgi?id=129
- - http://bugs.libre-riscv.org/show_bug.cgi?id=130
+### 2019-10P-032 28-apr-2020 - Paid 08may2020 
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=162> parent #196
+    - Verify FSGNJ
+    - EUR 150
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=163> parent #196
+    - Verify FPMAX/MIN
+    - EUR 150
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=165> parent #196
+    - Verify FP comparison operators
+    - EUR 150
 
-## Paid
 
 ### Project 2019-02-012 Date 27jan2020
 
- - http://bugs.libre-riscv.org/show_bug.cgi?id=120
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=120>
+
+### Project 2019-02-012 Date 09feb2020 - paid 28feb2020
+
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=129>
+   - Floating point eq, gt, ge
+   - EUR 150
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=130>
+   - Floating point min/max
+   - EUR 200