## Currently working on
- - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> with [[lkcl]]
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
+ - with [[lkcl]]
- <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
+ - functions needed for simulator
+ - Shared 90% with [[lkcl]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=211> parent #198
+ - Formal proof of decoder
+ - EUR 200
## Completed not yet submitted
-### 2019-02-012
+## Submitted for RFP, waiting for payment
+
+### 2019-02-012 28-apr-2020
- <http://bugs.libre-riscv.org/show_bug.cgi?id=189> parent #48
- Add partitioned right shift to partitioned shifter
- Shared 50% with [[lkcl]]
- EUR 350 (each)
-### 2019-10P-046
+### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
- - <https://bugs.libre-soc.org/show_bug.cgi?id=269>
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
- auto-parser of POWER9
- Shared 50% with [[lkcl]]
- - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
- - functions needed for simulator
- - Shared 90% with [[lkcl]]
+ - EUR 500 (each)
-### 2019-10P-032
+### 2019-10P-032 28-apr-2020 NLNet 2019 Formal Correctness Proofs
- - <https://bugs.libre-soc.org/show_bug.cgi?id=162>
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=162> parent #196
- Verify FSGNJ
- - <https://bugs.libre-soc.org/show_bug.cgi?id=163>
+ - EUR 150
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=163> parent #196
- Verify FPMAX/MIN
- - <https://bugs.libre-soc.org/show_bug.cgi?id=165>
+ - EUR 150
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=165> parent #196
- Verify FP comparison operators
- - <https://bugs.libre-soc.org/show_bug.cgi?id=211>
- - Formal proof of decoder
-
-## Submitted for RFP, waiting for payment
+ - EUR 150