-# NL.net proposal
+# NLnet.net LIP6.fr Coriolis2 proposal
+
+* [[questions]]
+* approved 20dec2019
+* MOU TBD
+* NLNet Project Page <https://nlnet.nl/project/Coriolis2/>
## Project name
rather than pay for proprietary software that, apart from being incredibly
expensive, could potentially compromise the integrity of the project.
-We therefore intend to collaborate with engineers from the Laboratoire
-d'Informatique de Paris 6, to use and improve their VLSI Layout tool,
-Coriolis2, in conjunction with Chips4Makers, to create the layout that
-Chips4Makers will then put into a 180nm 300mhz test chip.
+We therefore intend to collaborate with engineers from LIP6, to use
+and improve their VLSI Layout tool, Coriolis2, in conjunction with
+Chips4Makers, to create the layout that Chips4Makers will then put into
+a 180nm 300mhz test chip.
# Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
lead developer on the Libre RISC-V SoC.
Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2
-tools for VLSI backend layout, from the Laboratoire d'Informatique de
-Paris 6.
+tools for VLSI backend layout, from LIP6.
# Requested Amount
-EUR $50,000.
+EUR 50,000.
# Explain what the requested budget will be used for?
* Essential augmentations to nmigen to make it ASIC-layout-capable
All of these will be and are entirely libre-licensed software: there will
-be no proprietary software tools utilised in this process. Note that
+be no proprietary software tools utilised in this process.
# Does the project have other funding sources, both past and present?
## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
-We have a pre-launch Crowdsupply page up and running already, at
-https://www.crowdsupply.com/libre-risc-v/m-class through which we will
-engage with developers and end-users alike. Developers will be invited
-to participate through the http://libre-riscv.org website and resources.
+LIP6 have their own mailing list for the (transparent) discussion of
+issues related to coriolis2: <alliance-users@asim.lip6.fr>. The Libre RISC-V
+SoC has a full set of resources for Libre Project Management and development:
+mailing list, bugtracker, git repository and wiki - all listed here:
+<https://libre-riscv.org/>
-The Crowdsupply page has already been picked up by Phoronix, Heise.de
-Magazine, reddit and ycombinator. There is a lot of interest in this
-project.
+In addition, we have a Crowdsupply page
+<https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
+gateway, and heise.de, reddit, phoronix, slashdot and other locations have
+all picked up the story. The list is updated and maintained here:
+<https://libre-riscv.org/3d_gpu/>
# Extra info to be submitted
-* <https://hardware.slashdot.org/story/18/12/11/1410200/super-micro-says-review-found-no-malicious-chips-in-motherboards>
-* <https://libreboot.org/faq.html#intelme>
+* <http://libre-riscv.org/3d_gpu/>
+* <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
+* <https://nlnet.nl/project/Libre-RISCV/>
+* <https://chips4makers.io/blog/>
+