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[libreriscv.git] / nlnet_2019_coriolis2.mdwn

diff --git a/nlnet_2019_coriolis2.mdwn b/nlnet_2019_coriolis2.mdwn
index 7966496b6791590bbc03d28399956c631e9e29ed..c6b5e69f0f341c110733fb659a1ddbb3e429f62f 100644 (file)
--- a/nlnet_2019_coriolis2.mdwn
+++ b/nlnet_2019_coriolis2.mdwn
@@ -29,10 +29,10 @@ It is necessary, therefore, to use libre-licensed VLSI Layout tools
 rather than pay for proprietary software that, apart from being incredibly
 expensive, could potentially compromise the integrity of the project.
 
-We therefore intend to collaborate with engineers from the Laboratoire
-d'Informatique de Paris 6, to use and improve their VLSI Layout tool,
-Coriolis2, in conjunction with Chips4Makers, to create the layout that
-Chips4Makers will then put into a 180nm 300mhz test chip.
+We therefore intend to collaborate with engineers from LIP6, to use
+and improve their VLSI Layout tool, Coriolis2, in conjunction with
+Chips4Makers, to create the layout that Chips4Makers will then put into
+a 180nm 300mhz test chip.
 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 
@@ -42,12 +42,11 @@ Luke Leighton is an ethical technology specialist who has a consistent
 lead developer on the Libre RISC-V SoC.
 
 Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2
-tools for VLSI backend layout, from the Laboratoire d'Informatique de
-Paris 6.
+tools for VLSI backend layout, from LIP6.
 
 # Requested Amount    
 
-EUR $50,000.
+EUR 50,000.
 
 # Explain what the requested budget will be used for? 
 
@@ -86,7 +85,7 @@ So therefore, the requested budget will be used for:
 * Essential augmentations to nmigen to make it ASIC-layout-capable
 
 All of these will be and are entirely libre-licensed software: there will
-be no proprietary software tools utilised in this process.  Note that
+be no proprietary software tools utilised in this process.
 
 
 # Does the project have other funding sources, both past and present?