-# NL.net proposal
+# NLnet.net LIP6.fr Coriolis2 proposal
+
+* [[questions]]
+* approved 20dec2019
+* MOU TBD
+* 2019-10-029
+* NLNet Project Page <https://nlnet.nl/project/Coriolis2/>
+* Top-level bugreport <http://bugs.libre-riscv.org/show_bug.cgi?id=138>
## Project name
rather than pay for proprietary software that, apart from being incredibly
expensive, could potentially compromise the integrity of the project.
-We therefore intend to collaborate with engineers from the Laboratoire
-d'Informatique de Paris 6, to use and improve their VLSI Layout tool,
-Coriolis2, in conjunction with Chips4Makers, to create the layout that
-Chips4Makers will then put into a 180nm 300mhz test chip.
+We therefore intend to collaborate with engineers from LIP6, to use
+and improve their VLSI Layout tool, Coriolis2, in conjunction with
+Chips4Makers, to create the layout that Chips4Makers will then put into
+a 180nm 300mhz test chip.
# Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
lead developer on the Libre RISC-V SoC.
Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2
-tools for VLSI backend layout, from the Laboratoire d'Informatique de
-Paris 6.
+tools for VLSI backend layout, from LIP6.
# Requested Amount
-EUR $50,000.
+EUR 50,000.
# Explain what the requested budget will be used for?
* Essential augmentations to nmigen to make it ASIC-layout-capable
All of these will be and are entirely libre-licensed software: there will
-be no proprietary software tools utilised in this process. Note that
+be no proprietary software tools utilised in this process.
# Does the project have other funding sources, both past and present?