clarify

[libreriscv.git] / nlnet_2022_librebmc.mdwn

diff --git a/nlnet_2022_librebmc.mdwn b/nlnet_2022_librebmc.mdwn
index 5699edd8489fce41c5cd8bd76a313b8ef97ad00f..9369d8ae087588b8a6a66d90c4a9a435468b7b34 100644 (file)
--- a/nlnet_2022_librebmc.mdwn
+++ b/nlnet_2022_librebmc.mdwn
@@ -20,21 +20,24 @@ if you need any HTML to make your point please include this as attachment.
 
 ## Abstract: Can you explain the whole project and its expected outcome(s).
 
-LibreBMC replaces the proprietary Boot Management Controller and its
+LibreBMC replaces the proprietary Base board Management Controller (BMC) and its
 secret firmware, entirely. In servers typically used in Data Centres
 and for scenarios where data privacy is paramount
 this turns out to be critical.  One of the most commonly-used BMC
 Processors in the world has a silicon-baked plaintext password for its
 Serial Console, and with a BMC being the very means by which
-a processor's BIOS is uploaded it allows full bypass of every conceivable
+a processor's BIOS is uploaded, this publicly-available password
+allows for a full bypass of every conceivable
 security measure.
 
 BMC Processors are also present in every AMD and Intel desktop and Laptop
 in the world.  Even replacing the BIOS with coreboot is not enough to
-gain trust because the BMC is in charge of uploading coreboot.
+gain trust because the BMC is in charge of uploading coreboot, and could
+easily alter it.
 At least in this case if the BMC's firmware is replaced it increases
 trust that the payload (coreboot) has not been tampered with. However
-this is so low-level that there is serious risk of damaging the machine.
+this is so low-level that there is serious risk of damaging the user's
+machine.
 
 LibreBMC therefore intends to make a low-cost dual FPGA-based "Experimentation"
 platform, as Libre/Open Hardware, for developers to iteratively
@@ -43,19 +46,33 @@ without risk of damage to the machine it is managing.  One FPGA will
 run LibreBMC, the other Libre-SOC/Microwatt/A2O, and the first will boot
 the second.
 
+This will allow the next phase - actual booting of servers and desktop
+machines - to proceed with confidence.
 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 
 
 # Requested Amount    
 
-EUR 750,000.
+EUR 75,000.
 
 # Explain what the requested budget will be used for? 
 
+* Design and fabrication of Libre/Open Hardware Dual FPGA Carrier
+  boards (most likely accepting OrangeCrab as a module)
+* Porting of both LibreBMC and OpenBMC to the FPGA Board
+* Porting to Raptor Engineering's Arctic Tern Board
+* Implementation of *server* side LPC (client-side already exists)
+* Verilator simulation of both client and server side LPC
+  and testing of the two simulations back-to-back
+* Development of an EU Standard for Baseboard Management Control,
+  suitable for EU end-user products such as chromebooks, laptops,
+  and desktop computers (instead of the current soldered-down
+  insecure ICs).
 
 # Compare your own project with existing or historical efforts.
 
+TODO compare with RunBMC and OpenBMC.
 
 ## What are significant technical challenges you expect to solve during the project, if any?