+# 20th Sep 2023
+
+*(Diagram updated: 11th Oct 2023)*
+
+Current diagram for ongoing grant, no changes made anywhere.
+
+ Bug 961 - NLnet 2022 Libre-SOC "ongoing" milestone 2022-08-107 (approved, MoU TBD) - 100000
+ |
+ |-- (NOT STARTED) Bug 1036 - Formal Proof for LDSTCompUnit is needed - 3000
+ |
+ |-- (DONE) Bug 999 - SFFS Operating System Porting - 10000
+ |
+ |-| (IN PROGRESS) Bug 1003 - instruction database continuation and binutils, SVP64 - 10500
+ | |- (DONE) Bug 1068 - add instructions from ls012 not currently implemented in binutils - 3800
+ | |- (IN PROGRESS) Bug 1079 - make LD/ST-with-update EXTRA3 - 2000
+ | |- (ABSOLUTE TOP PRIORITY TO BE COMPLETED AS ABOLUTE CRITICAL WORK) Bug 1083 - update to DD FFirst Mode binutils PowerDecoder - 700
+ | | Comment #13 REQUESTS cancelling BUT IS DENIED AND NOT AUTHORIZED.
+ | |- (DONE) Bug 1094 - insndb instruction database visitor-walker is needed - 4000
+ |
+ |-- (NOT STARTED) Bug 1024 - Second phase of nmigen Dynamic Partitioned SIMD and nmigen language improvements - 6000
+ |
+ |-| (IN PROGRESS) Bug 1026 - implement Draft Instructions in nmigen HDL - 8000
+ | |- (DONE) Bug 1072 - implement fcvt/fmv instructions in ISACaller (ls006) - 3000
+ | |- Unallocated 5000EUR
+ |
+ |-| (IN PROGRESS) Bug 1027 - implement "necessary" additions to SVP64 and Scalar Power ISA - 24000
+ | |- (CONFIRMED, NOT STARTED) Bug 852 - implement grevlut* - 2000
+ | |- (DONE) Bug 972 - addme/subfme carry/overflow is incorrect - 1000
+ | |- (DONE) Bug 1028 - implement integer-versions of fft/dct "butterfly" instructions in ISACaller Simulator - 4000
+ | |- (DONE) Bug 1030 - Enable compilation of PyPowersim on non-power platforms. - 2000
+ | |- (CONFIRMED, NOT STARTED) Bug 1031 - implement CRweird instructions in ISACaller - 3000
+ | |- (CONFIRMED, NOT STARTED) Bug 1034 - implement crternlogi crbinlut and binlut in ISACaller - 3000
+ | |- (IN PROGRESS) Bug 1047 - SVP64 LD/ST Data-Dependent Fail-First providing linked-list walking - 3000
+ | |- (IN PROGRESS) Bug 1061 - change extsb/h/w definitions to scale input size with XLEN rather than convert from fixed sizes - 1000
+ | |- (DONE) Bug 1064 - Change XLEN-ification - 1000
+ | |- (CONFIRMED, IN PROGRESS) Bug 1071 - add parallel prefix sum remap mode - 2000
+ | |- (CONFIRMED, IN PROGRESS) Bug 1116 - evaluate, spec, and implement Vector-Immediates in SVP64 Normal - 2000
+ |
+ |-- (CONFIRMED, NOT STARTED) Bug 1032 - Implementation of SVP64 features: elwidth overrides and REMAP - 8000
+ |
+ |-- (CONFIRMED, NOT STARTED) Bug 1033 - Implementation and enhancement of "Test API" - 2500
+ |
+ |-| (IN PROGRESS) Bug 1035 - Implement Scalar Power ISA v3.1 (32-bit-only) instructions (no PO1) in ISACaller - 7000
+ | |- (DONE) Bug 1120 - Add all scalar 32-bit v3.1 insns to ISACaller - 2000
+ | |- (CONFIRMED, NOT STARTED) Bug 1147 - support Scalar Power ISA v3.1 (32-bit-only) instructions (no PO1) in binutils - 1000
+ |
+ |-| (CONFIRMED, NOT STARTED) Bug 1037 - improvements of Libre-SOC core support on FPGA boards - 6000
+ | |- (CONFIRMED, IN PROGRESS) Bug 990 - gram needs changes to work on the orangecrab - 4500
+ | |- (CONFIRMED, IN PROGRESS) Bug 1004 - FPGA bring up for platform definitions - 1500
+ |
+ |-- (IN PROGRESS) Bug 1039 - add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core - 3000
+ |
+ |-- (CONFIRMED, NOT STARTED) Bug 1150 - implement PO9 changeover and associated tasks - 8000
+
+
+# Meeting 30th aug 2023 16:00 UTC
+
+* Checked TOML fields and participants in bugs: 961, 1035, 1068, 1083, 1119, 1120, 1123,
+1146, 1147, 1148
+
+**TODO**: Check unallocated budget for bugs 737, 1035, 1026. Also check bug 1047 budget
+allocation.
+
+# Meeting 30th aug 2023 08:45 UTC
+
+* Updated the TOML fields for the following bugs: 737, 852, 990, 999, 1004, 1024, 1025,
+1026, 1031, 1032, 1033, 1034, 1035, 1039, 1086, 1116, 1120, 1123, 1128, 1130, 1131, 1132
+
+* If Dmitriy has any more ammendments to make, please check your subtasks (we didn't
+see any problems).
+
+* Jacob please update the json file.
+
+* Luke (once checked with Dmitry and Jacob) please do a final check and submit.
+
+**TODO**: Dmitry would like to make budget adjustments to
+[bug #1068](https://bugs.libre-soc.org/show_bug.cgi?id=1068),
+a subtask of [bug #1003](https://bugs.libre-soc.org/show_bug.cgi?id=1003).
+See the
+[IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-30.log.html#t2023-08-30T11:18:53)
+
+* A meeting later today will be arranged to make adjustments to the budget.
+
+Edit:
+
+* [Bug #1116](https://bugs.libre-soc.org/show_bug.cgi?id=1116#c7) only needs one person to do the work, so budget allocation adjusted accordingly.
+
+* Need a discussion on [bug #1047](https://bugs.libre-soc.org/show_bug.cgi?id=1047#c10), as it also intended to done by one person.
+
+* Jacob mentioned to re-adjust
+[bug #1123](https://bugs.libre-soc.org/show_bug.cgi?id=1123#c3) budget to about
+half of bug #1120. Also Dmitry is not involved in this task (his work will be on a subtask
+bug #1035).
+
# questions 17 aug 2023
* <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>
before #1003).
* "observe in the child tasks that the entire budget *has* already been allocated to subtasks.... *none of which* overlap (or are a duplicate of) #972"
* Bug #1003 does however build on the work from #972.
+* Added to comment 0 of bug #1003 to clarify that it builds on top of #972.
+
+**TODO: just put clear message describing task. No "Edit: this etc etc"**
+
+* Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).
+
+**TODO: 1) the 1st sentence does not mention binutils. 2. it needs to say "continuation of bug #976"
+ 3. a "--" is needed. 4. the paragraph "this is an umbrella task" is unnecessary. we already know it's an umbrella task, as it has child
+subtasks. 5. the last sentence which repeats for the *third* or fourth time "this is a task" can be removed. 6. again "bug #976" not "#976".**
+
+* Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).
### Bug #999
Gentoo/Debian pages) a wiki page describing the
work he went through with qemu.
+**TODO: sadoon, edit the "TODOs" and "DONEs" to include the relevant bugreports.**
+
+**TODO: sadoon, complete the descriptions in comment zeros of each subtask of #999.**
+
+* Edit: Sadoon updated comments 0 for bugs #999, 1130, 1131, 1132.
+
### Bugs 1025/1026
* Jacob is still working on figuring out the subtasks which should be focused
on for the scope of the On-Going grant.
+**NOT NEEDED at this stage, can be submitted later. we need to MOVE and get the MoU signed**
+
+Edit: Jacob specified that 1025/1026 subtasks are not going to be part of
+the MoU. See
+[IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-24.log.html#t2023-08-24T17:27:20)
+
+**please REMOVE that. it is NOT necessary to make such a statement.
+it is already known**
+
+### Bug 1032
+
+* Jacob mentioned there are two major parts
+
+1. Decoder/fetch pipeline
+2. Execution unit
+
+Cesar likely do the former, Jacob could do the latter.
+
+**CORRECTION: JACOB to do both.**
+
+* Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1032#c0).
+
+### Bug 1033
+
+* Create the framework for testing (or choose existing)
+ (jacob: important clarification -- afaict this task is adding new `StateRunner`
+ and `State` subclasses for FPGA/verilator/etc.
+ This task is *not* for creating a new framework or choosing an existing framework,
+ we already have one with implementations for pypowersim, nmigen simulation of the
+ libre-soc core, and `ExpectedState`. maybe also QEMU through GDB, icr.)
+* Add specialisation for pypowersim, microwatt (verilator), FPGA.
+* Cavatools out of scope.
+* Builds on top of <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=c23202498ae30addf04ab4c1e0d7262cc825cd45>?
+* Initially pypowersim tested against qemu, then FPGA.
+* For Simple-V/SVP64 only pypowersim implementation right now.
+SoC HDL has small subset of SVP64.
+
+
+### Automated method for removing non-MOU things
+
+* Jacob added a feature to automatically remove non-MOU strings.
+
+**(and didn't follow instructions which was to only add support for "--...--" the standard line-break of markdown). now additional work has to be done looking for the extremely irritating and tiresome and completely undocumented "trigger-sentence" which if typed incorrectly will not do its job)**
+
# questions 05 oct 2022
context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
projects / libreriscv.git / blobdiff