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[libreriscv.git] / nlnet_2022_ongoing / discussion.mdwn

diff --git a/nlnet_2022_ongoing/discussion.mdwn b/nlnet_2022_ongoing/discussion.mdwn
index aa9c3f850ed956501d870e3db8e05847d4d05aaf..7e567129f693a57850178fb44c0c63d930216a4d 100644 (file)
--- a/nlnet_2022_ongoing/discussion.mdwn
+++ b/nlnet_2022_ongoing/discussion.mdwn
@@ -18,7 +18,8 @@ group backed by Intel!)
 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
 * 3-4 months: Addition of the IEEE754 FPU to the Core
 * 3-4 months: Addition of other ALUs and pipelines
-* 4-5 months: Addition of SMP (multi-core) support (lots of research here)
+* 4-5 months: Addition of SMP (multi-core) support (lots of research here,
+  need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
 * 3-4 months: Running under Verilator and on FPGAs (big ones) 
 * 4-5 months: Continued documentation, attendance of Conferences online
 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
@@ -30,6 +31,10 @@ budget @ EUR 3,000/mo is within target (just). may need adjusting or some
 tasks removing, to fit. we cannot risk committing to tasks at too low a
 rate to be able to attract interest and committment.
 
+Again however I do not have a problem with reducing the scope of this one
+to only EUR 50,000 to cover some of the less ambitious tasks, and the
+necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) first.
+
 **
     What would be the concrete (high level) outcome of that project -
     where would the grant get us? Would there be a new test chip made