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[libreriscv.git] / nlnet_2022_opf_isa_wg.mdwn

diff --git a/nlnet_2022_opf_isa_wg.mdwn b/nlnet_2022_opf_isa_wg.mdwn
index e6f2253e50df08a240e38dc72728d36dff4984cd..a6f916fda171d32284dc20fea235c66faf243c52 100644 (file)
--- a/nlnet_2022_opf_isa_wg.mdwn
+++ b/nlnet_2022_opf_isa_wg.mdwn
@@ -44,7 +44,10 @@ as well as ongoing work on the Simulator.
 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 
-A lot! 
+A lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
+and includes the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma; the world's first in-place Discrete Cosine Transform algorithm;
+Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs) to do an 800,000 transistor fully automated RTL2GDSII
+tape-out; the side-benefits alone are enormous.
 
 # Requested Amount    
 
@@ -52,12 +55,6 @@ EUR 100,000.
 
 # Explain what the requested budget will be used for? 
 
-* Design and fabrication of Libre/Open Hardware Dual FPGA Carrier
-  boards (most likely accepting OrangeCrab as a module)
-* Porting of both LibreBMC and OpenBMC to the FPGA Board
-* Implementation of *server* side LPC (client-side already exists)
-* Verilator simulation of both client and server side LPC
-  and testing of the two simulations back-to-back
 
 # Compare your own project with existing or historical efforts.