change integer min/max to use (RA|0)

[libreriscv.git] / nlnet_2022_opf_isa_wg.mdwn

diff --git a/nlnet_2022_opf_isa_wg.mdwn b/nlnet_2022_opf_isa_wg.mdwn
index 86dff2a6eda6ad56d8be7168e3a8cd06aa0d0b53..ce5f72324835953aa23d068a8ec75ad9009aefc4 100644 (file)
--- a/nlnet_2022_opf_isa_wg.mdwn
+++ b/nlnet_2022_opf_isa_wg.mdwn
@@ -1,14 +1,33 @@
 # NL.net proposal
 
+* 2022-08-051, approved 24 Oct 2022
+* [[nlnet_2022_opf_isa_wg/discussion]]
+* <https://bugs.libre-soc.org/show_bug.cgi?id=952>
 
 ## Project name
 
-OpenPOWER ISA RFCs
+Libre-SOC OpenPOWER ISA RFCs
 
 ## Website / wiki 
 
 <https://libre-soc.org/nlnet_2022_opf_isa_wg>
 
+# Summary
+
+In earlier NLnet Grants, thanks to EU funding, we developed Draft
+SVP64 (a Vector Extension for the Power ISA), around a hundred
+new Draft instructions that dramatically improves the Supercomputing-class
+Power ISA, a Simulator, thousands
+of unit tests and over 350 pages of documentation.  What we could
+not do however was submit a Specification to the OpenPOWER ISA
+Working Group because the ISA WG was in the process of being
+ratified.  That has now been done, and we need to begin the
+formal process of writing up "Requests For Change" and submitting
+them. The end result will be an extremely powerful Vector ISA suitable
+for use in Digitally-Sovereign end-user products.
+
+# Submission to NLnet
+
 Please be short and to the point in your answers; focus primarily on
 the what and how, not so much on the why. Add longer descriptions as
 attachments (see below). If English isn't your first language, don't
@@ -92,7 +111,7 @@ transfer to the OpenPOWER Foundation.
 
 We are developing a Cray-style Scalable Vector ISA Extension for
 the Supercomputing-class Power ISA.  Similar historic ISAs include
-Cray YMP1, ETA-19, Cyber CDC 205. More recent is the NEC SX Aurora.
+Cray Y/MP, ETA-10, Cyber CDC 205. More recent is the NEC SX Aurora.
 They are all proprietary systems: Libre-SOC's efforts are entirely
 FOSSHW.