sync_up: Update my section

[libreriscv.git] / nlnet_proposals.mdwn

diff --git a/nlnet_proposals.mdwn b/nlnet_proposals.mdwn
index aebd4c9ba5eaaaf57529d4e726b90329d00016f6..4b1d69fbc31c748fabb78133d51d7b14c29be39c 100644 (file)
--- a/nlnet_proposals.mdwn
+++ b/nlnet_proposals.mdwn
@@ -7,8 +7,8 @@
 
 # being written
 
-* [[nlnet_2023_simplev_riscv_binutils]]
-* [[nlnet_2023_simplev_riscv]]
+* [[nlnet_2023_simplev_riscv_binutils]] - submitted 2023nov30 2023-12-121
+* [[nlnet_2023_simplev_riscv]] - submitted 2023nov24 2023-12-059 - submitter RED Semiconductor Ltd
 
 # completed