hdl.ast: rename `nbits` to `width`.

[nmigen.git] / nmigen / back / pysim.py

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 57461ee84c2e6f1861136ddc2233b35853eeda7b..0f7e8c0a0c191e49f8338732e216e2f8c9ed1c8c 100644 (file)
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -561,7 +561,7 @@ class Simulator:
                     var_init = signal.decoder(signal.reset).expandtabs().replace(" ", "_")
                 else:
                     var_type = "wire"
-                    var_size = signal.nbits
+                    var_size = signal.width
                     var_init = signal.reset
 
                 suffix = None