add more code

[nmigen-type-annotations.git] / nmigen / back / pysim.pyi

diff --git a/nmigen/back/pysim.pyi b/nmigen/back/pysim.pyi
index e797b5fe632495bd4b2832c00115a9869229f04f..b0254ea665c37ab0eadfc98061545c36d56b27c2 100644 (file)
--- a/nmigen/back/pysim.pyi
+++ b/nmigen/back/pysim.pyi
@@ -1,8 +1,8 @@
-from ..hdl.ast import (Signal, Statement, Delay as Delay,
+from ..hdl.ast import (Signal, Delay as Delay,
                        Tick as Tick, Passive as Passive, Assign, Value)
 from typing import Any, Iterable, Generator, Union, Callable, Optional
 
-__all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"]
+__all__ = ["Simulator", "Delay", "Tick", "Passive"]
 
 ProcessCommand = Union[Delay, Tick, Passive, Assign, Value]
 ProcessGenerator = Generator[ProcessCommand, Union[int, None], None]