back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion.

[nmigen.git] / nmigen / build / __init__.py

diff --git a/nmigen/build/__init__.py b/nmigen/build/__init__.py
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c4bc9f3dbc18a080b6e5ce2b51c6fe79aaeaf054 100644 (file)
--- a/nmigen/build/__init__.py
+++ b/nmigen/build/__init__.py
@@ -0,0 +1,3 @@
+from .dsl import *
+from .res import ResourceError
+from .plat import *