back.pysim: fix behavior of initial cycle for sync processes.
[nmigen.git] / nmigen / lib / fifo.py
index 6e8e67926b4bfaeaaaf7c57b0f27069952cdec44..e26d3d43becf1bc7e65134baa2ae723f882a01d5 100644 (file)
@@ -72,9 +72,9 @@ class FIFOInterface:
 
     def read(self):
         """Read method for simulation."""
+        assert (yield self.readable)
         yield self.re.eq(1)
         yield
-        assert (yield self.readable)
         value = (yield self.dout)
         yield self.re.eq(0)
         return value