hdl.{ast,dst}: directly represent RTLIL default case.

[nmigen.git] / nmigen / test / test_hdl_dsl.py

diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py
index 0e703e0c995b94db5fdef07830cae834318072ec..e15b1aacc769590edfbb62fddbcb99723005c021 100644 (file)
--- a/nmigen/test/test_hdl_dsl.py
+++ b/nmigen/test/test_hdl_dsl.py
@@ -174,7 +174,7 @@ class DSLTestCase(FHDLTestCase):
             (switch (cat (sig s1) (sig s2))
                 (case -1 (eq (sig c1) (const 1'd1)))
                 (case 1- (eq (sig c2) (const 1'd0)))
-                (case -- (eq (sig c3) (const 1'd1)))
+                (default (eq (sig c3) (const 1'd1)))
             )
         )
         """)
@@ -234,7 +234,7 @@ class DSLTestCase(FHDLTestCase):
                         (case 1 (eq (sig c2) (const 1'd1)))
                     )
                 )
-                (case -
+                (default
                     (eq (sig c3) (const 1'd1))
                 )
             )