back.pysim: synchronize waveform writing with cxxrtl.

[nmigen.git] / nmigen / test / test_sim.py

diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py
index adc6c260f00ee450e536050394d591c55ddb3af1..bff305129e54e47daba83ee3a80c6d259ed47226 100644 (file)
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@@ -777,18 +777,6 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
             with sim.write_vcd(open(os.path.devnull, "wt")):
                 pass
 
-    def test_vcd_wrong_twice(self):
-        s = Signal()
-        m = Module()
-        m.d.sync += s.eq(s)
-        sim = Simulator(m)
-        sim.add_clock(1e-6)
-        with self.assertRaisesRegex(ValueError,
-                r"^Already writing waveforms to .+$"):
-            with sim.write_vcd(open(os.path.devnull, "wt")):
-                with sim.write_vcd(open(os.path.devnull, "wt")):
-                    pass
-
 
 class SimulatorRegressionTestCase(FHDLTestCase):
     def test_bug_325(self):