+2002-09-20 Nick Clifton <nickc@redhat.com>
+
+ * ppc-opc.c (CRFD, CRFS): Add PPC_OPERAND_CR flag so that cr
+ register names are accepted.
+
+2002-09-17 Svein E. Seldal <Svein.Seldal@solidas.com>
+
+ * tic4x-dis.c: Add function declarations and ATTRIBUTE_UNUSED.
+ Convert functions to K&R format.
+
+2002-09-13 Nick Clifton <nickc@redhat.com>
+
+ * ppc-opc.c (MFDEC2): Include Book-E.
+ (PPCCHLK64): New opcode mask.
+ (evsubw, evsubiw, evmr, evnot, isellt, iselgt, iseleq, mfpid,
+ mfcsrr0, mfcsrr1, mfdear, mfesr, mfivpr, mfusprg0, mftbl,
+ mftbu, mfpir, mfdbsr, mfdbcr0, mfdbcr1, mfdbcr2, mfiac1,
+ mfiac2, mfiac3, mfiac4, mfdac1, mfdac2, mfdvc1, mfdvc2, mftsr,
+ mftcr, mfivor0, mfivor1, mfivor2, mfivor3, mfivor4, mfivor5,
+ mfivor6, mfivor7, mfivor8, mfivor9, mfivor10, mfivor11,
+ mfivor12, mfivor13, mfivor14, mfivor15, mfbbear, mfmcsrr0,
+ mfmcsrr1, mfmcsr, mtpid, mtdecar, mtcsrr0, mtcsrr1, mtdear,
+ mtesr, mtivpr, mtusprg0, mtsprg4, mtsprg5, mtsprg6, mtsprg7,
+ mtdbsr, mtdbcr0, mtdbcr1, mtdbcr2, mtiac1, mtiac2, mtiac3,
+ mtiac4, mtdac1, mtdac2, mtdvc1, mtdvc2, mttsr, mttcr, mtivor0,
+ mtivor1, mtivor2, mtivor3, mtivor4, mtivor5, mtivor6, mtivor7,
+ mtivor8, mtivor9, mtivor10, mtivor11, mtivor12, mtivor13,
+ mtivor14, mtivor15, mtbbear, mtmcsrr0, mtmcsrr1, mtmcsr): New
+ Book-E instructions.
+ (evfsneg): Fix opcode value.
+ (dcbtstlse, dcbtlse, icblce, dcblce, icbtsle): Use PPCCHLK64
+ mask.
+ (mcrxr64, tlbivaxe, tlbsxe, tlbsxe.): Restrict to 64-bit
+ Book-E.
+ (extsw): Restrict to 64-bit PPC instruction sets.
+ (extsw.): Does not exist in 64-bit Book-E.
+ (powerpc_macro): Remove mftbl, mftbu and mftb Book-E macros as
+ they are no longer needed.
+
+2002-09-12 Gary Hade <garyhade@us.ibm.com>
+
+ * ppc-dis.c (powerpc_dialect): Add missing PPC_OPCODE_CLASSIC.
+
+2002-09-11 Nick Clifton <nickc@redhat.com>
+
+ * po/da.po: Updated Danish translation file.
+
+2002-09-04 Nick Clifton <nickc@redhat.com>
+
+ * ppc-opc.c (extsw, extsw.): Do not allow for the BookE32.
+
+2002-09-04 Nick Clifton <nickc@redhat.com>
+
+ * disassemble.c (disassembler_usage): Add invocation of
+ print_ppc_disassembler_options.
+ * ppc-dis.c (print_ppc_disassembler_options): New function.
+
+2002-09-04 Nick Clifton <nickc@redhat.com>
+
+ * ppc-opc.c: The BookE implementations of the TLBWE and TLBRE
+ instructions do not take any arguments.
+
+2002-09-02 Nick Clifton <nickc@redhat.com>
+
+ * v850-opc.c: Remove redundant references to V850EA architecture.
+
+2002-09-02 Alan Modra <amodra@bigpond.net.au>
+
+ * arc-opc.c: Include bfd.h.
+ (arc_get_opcode_mach): Subtract off base bfd_mach value.
+
+2002-08-30 Alan Modra <amodra@bigpond.net.au>
+
+ * v850-dis.c (disassemble): Remove bfd_mach_v850ea case.
+
+ * mips-dis.c (_print_insn_mips): Don't use hard-coded mach constants.
+
+2002-08-28 Svein E. Seldal <Svein.Seldal@solidas.com>
+
+ * configure.in: Added bfd_tic4x_arch.
+ * configure: Regenerate.
+ * Makefile.am: Added tic4x-dis.o target.
+ * Makefile.in: Regenerate.
+
+2002-08-28 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
+
+ * disassemble.c: Added tic4x target and c4x
+ disassembler routine.
+ * tic4x-dis.c: New file.
+
+2002-08-16 Christian Groessler <chris@groessler.org>
+
+ * z8k-dis.c (unparse_instr): case CLASS_BA: Designate hex
+ values as those.
+ * z8kgen.c (opt): Fix definition of "in rd,imm16" opcode.
+ * z8k-opc.h: Regenerated with new z8kgen.c.
+
+2002-08-19 Elena Zannoni <ezannoni@redhat.com>
+
+ From matthew green <mrg@redhat.com>
+
+ * ppc-dis.c (powerpc_dialect): Support `-m500', `-m500x2' and
+ `-mefs'. Turn off AltiVec for E500 and efs.
+ (print_insn_powerpc): Don't print an AltiVec instruction if the
+ dialect is not efs.
+
+ * ppc-opc.c (insert_pmrn, extract_pmrn, insert_ev2, extract_ev2,
+ insert_ev4, extract_ev4, insert_ev8, extract_ev8): New functions
+ for extracting pmrn/evld/evstd/etc operands.
+ (CRB, CRFD, CRFS, DC, RD): New instruction fields.
+ (CT): Make this equal to RD + 1.
+ (PMRN): New operand.
+ (RA): Update.
+ (EVUIMM, EVUIMM_2, EVUIMM_4, EVUIMM_8): New operands.
+ (WS): Update.
+ (EVSEL, EVSEL_MASK): New instruction form and mask for EVSEL.
+ (ISEL, ISEL_MASK): New instruction form and mask for ISEL.
+ (XISEL, XISEL_MASK): New instruction form and mask for ISEL.
+ (CTX, CTX_MASK): New instruction form and mask for context cache
+ instructions.
+ (UCTX, UCTX_MASK): New instruction form and mask for user context
+ cache instructions.
+ (XC, XC_MASK, XUC, XUC_MASK): New instruction forms.
+ (CLASSIC): New define.
+ (PPCESPE): New define.
+ (PPCISEL, , PPCBRLK, PPCPMR, PPCCHLK, PPCRFMI): New
+ defines for integer select, cache control, branch
+ locking, power management, cache locking and machine check
+ APU instructions, respectively.
+ (efsabs, efsnabs, efsneg, efsadd, efssub, efsmul,
+ efsdiv, efscmpgt, efscmplt, efscmpeq, efststgt, efststlt,
+ efststeq, efscfui, efsctuiz, efscfsi, efscfuf, efscfsf,
+ efsctui, efsctsi, efsctsiz, efsctuf, efsctsf,
+ evaddw, evaddiw, evsubfw, evsubifw, evabs, evneg, evextsb,
+ evextsh, evrndw, evcntlzw, evcntlsw, brinc, evand, evandc, evor,
+ evorc, evxor, eveqv, evnand, evnor, evrlw, evrlwi, evslw, evslwi,
+ evsrws, evsrwu, evsrwis, evsrwiu, evsplati, evsplatfi, evmergehi,
+ evmergelo, evmergehilo, evmergelohi, evcmpgts, evcmpgtu, evcmplts,
+ evcmpltu, evcmpeq, evsel, evldd, evlddx, evldw, evldwx, evldh,
+ evldhx, evlwhe, evlwhex, evlwhou, evlwhoux, evlwhos, evlwhosx,
+ evlwwsplat, evlwwsplatx, evlwhsplat, evlwhsplatx, evlhhesplat,
+ evlhhesplatx, evlhousplat, evlhousplatx, evlhossplat, evlhossplatx,
+ evstdd, evstddx, evstdw, evstdwx, evstdh, evstdhx, evstwwe,
+ evstwwex, evstwwo, evstwwox, evstwhe, evstwhex, evstwho, evstwhox,
+ evfsabs, evfsnabs, evfsneg, evfsadd, evfssub, evfsmul, evfsdiv,
+ evfscmpgt, evfscmplt, evfscmpeq, evfststgt, evfststlt, evfststeq,
+ evfscfui, evfsctuiz, evfscfsi, evfscfuf, evfscfsf, evfsctui,
+ evfsctsi, evfsctsiz, evfsctuf, evfsctsf, evsabs, evsnabs, evsneg,
+ evsadd, evssub, evsmul, evsdiv, evscmpgt, evsgmplt, evsgmpeq,
+ evststgt, evststlt, evststeq, evscfui, evscfsi, evscfuf, evscfsf,
+ evsctui, evsctuiz, evsctsi, evsctsiz, evsctuf, evsctsf, evmhossf,
+ evmhossfa, evmhosmf, evmhosmfa, evmhosmi, evmhosmia, evmhoumi,
+ evmhoumia, evmhessf, evmhessfa, evmhesmf, evmhesmfa, evmhesmi,
+ evmhesmia, evmheumi, evmheumia, evmhossfaaw, evmhossiaaw,
+ evmhosmfaaw, evmhosmiaaw, evmhousiaaw, evmhoumiaaw, evmhessfaaw,
+ evmhessiaaw, evmhesmfaaw, evmhesmiaaw, evmheusiaaw, evmheumiaaw,
+ evmhossfanw, evmhossianw, evmhosmfanw, evmhosmianw, evmhousianw,
+ evmhoumianw, evmhessfanw, evmhessianw, evmhesmfanw, evmhesmianw,
+ evmheusianw, evmheumianw, evmhogsmfaa, evmhogsmiaa, evmhogumiaa,
+ evmhegsmfaa, evmhegsmiaa, evmhegumiaa, evmhogsmfan, evmhogsmian,
+ evmhogumian, evmhegsmfan, evmhegsmian, evmhegumian, evmwhssf,
+ evmwhssfa, evmwhssfaa, evmwhssmaa, evmwhsmfaa, evmwhsmiaa,
+ evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, evmwhsmfan,
+ evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, evmwhgsmfaa,
+ evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, evmwhgsmian,
+ evmwhgumian, evmwhsmf, evmwhsmfa, evmshsmi, evmshsmia, evmshumi,
+ evmshumia, evmmlssf, evmmlssfa, evmwlsmf, evmwlsmfa, evmwlumi,
+ evmwlumia, evmwlssfaaw, evmwlssiaaw, evmwlsmfaaw, evmwlsmiaaw,
+ evmwlusiaaw, evmwlumiaaw, evmwissfanw, evmwissianw, evmwlsmfanw,
+ evmwlsmianw, evmwlusianw, evmwlumianw, evmwssf, evmwssfa,
+ evmwsmf, evmwsmfa, evmwsmi, evmwsmia, evmwumi, evmwumia,
+ evmwssfaa, evmwsmfaa, evmwsmiaa, evmwumiaa, evmwssfan, evmwsmfan,
+ evmwsmian, evmwumian, evaddssiaaw, evaddsmiaaw, evaddusiaaw,
+ evaddumiaaw, evsubfssiaaw, evsubfsmiaaw, evsubfusiaaw,
+ evsubfumiaaw, evmra, evdivws, evdivws): New e500x2 Core Complex
+ instructions.
+ (rfmci): New machine check APU instruction.
+ (isel): New integer select APU instructino.
+ (icbtls, icbtlse, icblc, icblce, dcbtls, dcbtlse, dcbtstls,
+ dcbtstlse, dcblc, dcblce): New cache control APU instructions.
+ (mtspefscr, mfspefscr): New instructions.
+ (mfpmr, mtpmr): New performance monitor APU instructions.
+ (savecontext): New context cache APU instructions.
+ (bblels, bbelr): New branch locking APU instructions.
+ (bblels, bbelr): New instructions.
+ (mftbl, mftbu, mftb): Set as CLASSIC instructions. Add BOOKE alias.
+
+2002-08-13 Stephane Carrez <stcarrez@nerim.fr>
+
+ * m68hc11-opc.c: Update call operand to accept the page definition.
+ Identify instructions that are branches and calls to generate a
+ RL_JUMP relocation.
+
+2002-08-13 Stephane Carrez <stcarrez@nerim.fr>
+
+ * m68hc11-dis.c (print_insn): Take into account 68HC12 memory
+ banks and fix disassembling of call instruction.
+ (print_indexed_operand): New param to tell whether
+ it was an indirect addressing operand (for disassembling call).
+
+2002-08-09 Nick Clifton <nickc@redhat.com>
+
+ * po/sv.po: Updated Swedish translation.
+
+2002-08-08 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
+
+ * mips-opc.c (mips_builtin_opcodes): Remove "dla" and "la" as
+ aliases to "daddiu" and "addiu".
+
+2002-07-30 Nick Clifton <nickc@redhat.com>
+
+ * po/sv.po: Updated Swedish translation.
+
2002-07-25 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.