Fix disassembly of RISC-V CSR instructions under -Mno-aliases

[binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1e5ca723106d0eef0898993f9f1ac5c2745b747a..04430d1c581b5cad0bc8711b595128e7ea7aabce 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,109 @@
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+       * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
+       INSN_ALIAS.
+
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+       * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
+       format.
+
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+       * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
+       XLEN when none is provided.
+
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+       * riscv-opc.c: Formatting fixes.
+
+2016-12-20  Alan Modra  <amodra@gmail.com>
+
+       * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
+       * Makefile.in: Regenerate.
+       * po/POTFILES.in: Regenerate.
+
+2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
+       Only examine ELF file structures here.
+
+2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
+       `bfd_mips_elf_get_abiflags' here.
+
+2016-12-16  Nick Clifton  <nickc@redhat.com>
+
+       * arm-dis.c (print_insn_thumb32): Fix compile time warning
+       computing value_in_comment.
+
+2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips-dis.c (mips_convert_abiflags_ases): New function.
+       (set_default_mips_dis_options): Also infer ASE flags from ELF
+       file structures.
+
+2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
+       header flag interpretation code.
+
+2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
+       `pinfo2' with SP-relative "sd" entries.
+
+2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
+       compact jumps.
+
+2016-12-13 Renlin Li <renlin.li@arm.com>
+
+       * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
+       qualifier.
+       (operand_general_constraint_met_p): Remove case for CP_REG.
+       (aarch64_print_operand): Print CRn, CRm operand using imm field.
+       * aarch64-tbl.h (QL_SYS): Use CR qualifier.
+       (QL_SYSL): Likewise.
+       (aarch64_opcode_table): Change CRn, CRm operand class and type.
+       * aarch64-opc-2.c : Regenerate.
+       * aarch64-asm-2.c : Likewise.
+       * aarch64-dis-2.c : Likewise.
+
+2016-12-12  Yao Qi  <yao.qi@linaro.org>
+
+       * rx-dis.c: Include <setjmp.h>
+       (struct private): New.
+       (rx_get_byte): Check return value of read_memory_func, and
+       call memory_error_func and OPCODES_SIGLONGJMP on error.
+       (print_insn_rx): Call OPCODES_SIGSETJMP.
+
+2016-12-12  Yao Qi  <yao.qi@linaro.org>
+
+       * rl78-dis.c: Include <setjmp.h>.
+       (struct private): New.
+       (rl78_get_byte): Check return value of read_memory_func, and
+       call memory_error_func and OPCODES_SIGLONGJMP on error.
+       (print_insn_rl78_common): Call OPCODES_SIGJMP.
+
+2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
+
+2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
+       than UINT.
+
+2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips-dis.c (print_insn_mips16): Use a tab rather than a space
+       to separate `extend' and its uninterpreted argument output.
+       Separate hexadecimal halves of undecoded extended instructions
+       output.
+
 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
 
        * mips-dis.c (print_mips16_insn_arg): Remove extraneous