+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
+
+2010-09-22 Robin Getz <robin.getz@analog.com>
+
+ * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
+ register values greater than 8.
+ (IS_RESERVEDREG, allreg, mostreg): New helpers.
+ (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
+ (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
+ (decode_CC2dreg_0): Check valid CC register number.
+
+2010-09-22 Robin Getz <robin.getz@analog.com>
+
+ * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
+
+2010-09-22 Robin Getz <robin.getz@analog.com>
+
+ * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
+ (reg_names): Likewise.
+ (decode_statbits): Likewise; while reformatting to make manageable.
+
+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
+ (decode_pseudoOChar_0): New function.
+ (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
+
+2010-09-22 Robin Getz <robin.getz@analog.com>
+
+ * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
+ LSHIFT instead of SHIFT.
+
+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (constant_formats): Constify the whole structure.
+ (fmtconst): Add const to return value.
+ (reg_names): Mark const.
+ (decode_multfunc): Mark s0/s1 as const.
+ (decode_macfunc): Mark a/sop as const.
+
+2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
+
+ * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
+
+2010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
+ "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
+
+2010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
+
+ * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
+ dlx_insn_type array.
+
+2010-08-31 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/11960
+ * i386-dis.c (sIv): New.
+ (dis386): Replace Iq with sIv on "pushT".
+ (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
+ (x86_64_table): Replace {T|}/{P|} with P.
+ (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
+ (OP_sI): Update v_mode. Remove w_mode.
+
+2010-08-27 Nathan Froyd <froydnj@codesourcery.com>
+
+ * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
+ on E500 and E500MC.
+
+2010-08-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
+ prefetchw.
+
+2010-08-06 Quentin Neill <quentin.neill@amd.com>
+
+ * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
+ to processor flags for PENTIUMPRO processors and later.
+ * i386-opc.h (enum): Add CpuNop.
+ (i386_cpu_flags): Add cpunop bit.
+ * i386-opc.tbl: Change nop cpu_flags.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2010-08-06 Quentin Neill <quentin.neill@amd.com>
+
+ * i386-opc.h (enum): Fix typos in comments.
+
+2010-08-06 Alan Modra <amodra@gmail.com>
+
+ * disassemble.c: Formatting.
+ (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
+
+2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
+ * i386-tbl.h: Regenerated.
+
+2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
+
+ * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
+ * i386-tbl.h: Regenerated.
+
2010-07-29 DJ Delorie <dj@redhat.com>
* rx-decode.opc (SRR): New.
(rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
r0,r0) and NOP3 (max r0,r0) special cases.
* rx-decode.c: Regenerate.
-
+
2010-07-28 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c: Add 0F to VEX opcode enums.