+2021-06-03 Alan Modra <amodra@gmail.com>
+
+ PR 1202
+ * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
+ Use unsigned int for inst.
+
+2021-06-02 Shahab Vahedi <shahab@synopsys.com>
+
+ * arc-dis.c (arc_option_arg_t): New enumeration.
+ (arc_options): New variable.
+ (disassembler_options_arc): New function.
+ (print_arc_disassembler_options): Reimplement in terms of
+ "disassembler_options_arc".
+
+2021-05-29 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
+ Don't special case PPC_OPCODE_RAW.
+ (lookup_prefix): Likewise.
+ (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
+ (print_insn_powerpc): ..update caller.
+ * ppc-opc.c (EXT): Define.
+ (powerpc_opcodes): Mark extended mnemonics with EXT.
+ (prefix_opcodes, vle_opcodes): Likewise.
+ (XISEL, XISEL_MASK): Add cr field and simplify.
+ (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
+ all isel variants to where the base mnemonic belongs. Sort dstt,
+ dststt and dssall.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
+ COP3 opcode instructions.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
+ "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
+ "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
+ "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
+ "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
+ "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
+ "cop2", and "cop3" entries.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
+ entries and associated comments.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
+ of "c0".
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-dis.c (mips_cp1_names_mips): New variable.
+ (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
+ for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
+ "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
+ "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
+ "r12000", "r14000", "r16000", "mips5", "loongson2e", and
+ "loongson2f".
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
+ handling code over to...
+ <OP_REG_CONTROL>: ... this new case.
+ * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
+ (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
+ "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
+ replacing the `G' operand code with `g'. Update "cftc1" and
+ "cftc2" entries replacing the `E' operand code with `y'.
+ * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
+ (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
+ entries replacing the `G' operand code with `g'.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-dis.c (mips_cp0_names_r3900): New variable.
+ (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
+ for "r3900".
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
+ and "mtthc2" to using the `G' rather than `g' operand code for
+ the coprocessor control register referred.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
+ entries with each other.
+
+2021-05-27 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
+
+2021-05-25 Alan Modra <amodra@gmail.com>
+
+ * cris-desc.c: Regenerate.
+ * cris-desc.h: Regenerate.
+ * cris-opc.h: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2021-05-24 Mike Frysinger <vapier@gentoo.org>
+
+ * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
+ (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
+ (CGEN_CPUS): Add cris.
+ (CRIS_DEPS): Define.
+ (stamp-cris): New rule.
+ * cgen.sh: Handle desc action.
+ * configure.ac (bfd_cris_arch): Add cris-desc.lo.
+ * Makefile.in, configure: Regenerate.
+
+2021-05-18 Job Noorman <mtvec@pm.me>
+
+ PR 27814
+ * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
+ the elf objects.
+
+2021-05-17 Alex Coplan <alex.coplan@arm.com>
+
+ * arm-dis.c (mve_opcodes): Fix disassembly of
+ MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
+ (is_mve_encoding_conflict): MVE vector loads should not match
+ when P = W = 0.
+ (is_mve_unpredictable): It's not unpredictable to use the same
+ source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
+
+2021-05-11 Nick Clifton <nickc@redhat.com>
+
+ PR 27840
+ * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
+ the end of the code buffer.
+
+2021-05-06 Stafford Horne <shorne@gmail.com>
+
+ PR 21464
+ * or1k-asm.c: Regenerate.
+
+2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
+
+ * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
+ info->insn_info_valid.
+
+2021-04-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (lea): Add Optimize.
+ * opcodes/i386-tbl.h: Re-generate.
+
+2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
+
+ * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
+ of l32r fetch and display referenced literal value.
+
+2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
+
+ * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
+ to 4 for literal disassembly.
+
+2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
+ for TLBI instruction.
+
+2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
+ DC instruction.
+
+2021-04-19 Jan Beulich <jbeulich@suse.com>
+
+ * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
+ "qualifier".
+ (convert_mov_to_movewide): Add initializer for "value".
+
+2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add RME system registers.
+
+2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
+
+ * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
+ "addi d,CV,z" to "c.mv d,CV".
+
+2021-04-12 Alan Modra <amodra@gmail.com>
+
+ * configure.ac (--enable-checking): Add support.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+
+2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
+
+ * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
+ LD64/ST64 instructions to lse_atomic instead of ldstexcl.
+
+2021-04-09 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (struct dis_private): Add "special".
+ (POWERPC_DIALECT): Delete. Replace uses with..
+ (private_data): ..this. New inline function.
+ (disassemble_init_powerpc): Init "special" names.
+ (skip_optional_operands): Add is_pcrel arg, set when detecting R
+ field of prefix instructions.
+ (bsearch_reloc, print_got_plt): New functions.
+ (print_insn_powerpc): For pcrel instructions, print target address
+ and symbol if known, and decode plt and got loads too.
+
+2021-04-08 Alan Modra <amodra@gmail.com>
+
+ PR 27684
+ * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
+
2021-04-08 Alan Modra <amodra@gmail.com>
PR 27676
projects / binutils-gdb.git / blobdiff