+2021-06-03 Alan Modra <amodra@gmail.com>
+
+ PR 1202
+ * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
+ Use unsigned int for inst.
+
+2021-06-02 Shahab Vahedi <shahab@synopsys.com>
+
+ * arc-dis.c (arc_option_arg_t): New enumeration.
+ (arc_options): New variable.
+ (disassembler_options_arc): New function.
+ (print_arc_disassembler_options): Reimplement in terms of
+ "disassembler_options_arc".
+
+2021-05-29 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
+ Don't special case PPC_OPCODE_RAW.
+ (lookup_prefix): Likewise.
+ (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
+ (print_insn_powerpc): ..update caller.
+ * ppc-opc.c (EXT): Define.
+ (powerpc_opcodes): Mark extended mnemonics with EXT.
+ (prefix_opcodes, vle_opcodes): Likewise.
+ (XISEL, XISEL_MASK): Add cr field and simplify.
+ (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
+ all isel variants to where the base mnemonic belongs. Sort dstt,
+ dststt and dssall.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
+ COP3 opcode instructions.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
+ "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
+ "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
+ "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
+ "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
+ "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
+ "cop2", and "cop3" entries.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
+ entries and associated comments.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
+ of "c0".
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-dis.c (mips_cp1_names_mips): New variable.
+ (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
+ for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
+ "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
+ "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
+ "r12000", "r14000", "r16000", "mips5", "loongson2e", and
+ "loongson2f".
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
+ handling code over to...
+ <OP_REG_CONTROL>: ... this new case.
+ * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
+ (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
+ "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
+ replacing the `G' operand code with `g'. Update "cftc1" and
+ "cftc2" entries replacing the `E' operand code with `y'.
+ * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
+ (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
+ entries replacing the `G' operand code with `g'.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-dis.c (mips_cp0_names_r3900): New variable.
+ (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
+ for "r3900".
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
+ and "mtthc2" to using the `G' rather than `g' operand code for
+ the coprocessor control register referred.
+
+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
+ entries with each other.
+
+2021-05-27 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
+
+2021-05-25 Alan Modra <amodra@gmail.com>
+
+ * cris-desc.c: Regenerate.
+ * cris-desc.h: Regenerate.
+ * cris-opc.h: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2021-05-24 Mike Frysinger <vapier@gentoo.org>
+
+ * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
+ (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
+ (CGEN_CPUS): Add cris.
+ (CRIS_DEPS): Define.
+ (stamp-cris): New rule.
+ * cgen.sh: Handle desc action.
+ * configure.ac (bfd_cris_arch): Add cris-desc.lo.
+ * Makefile.in, configure: Regenerate.
+
+2021-05-18 Job Noorman <mtvec@pm.me>
+
+ PR 27814
+ * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
+ the elf objects.
+
+2021-05-17 Alex Coplan <alex.coplan@arm.com>
+
+ * arm-dis.c (mve_opcodes): Fix disassembly of
+ MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
+ (is_mve_encoding_conflict): MVE vector loads should not match
+ when P = W = 0.
+ (is_mve_unpredictable): It's not unpredictable to use the same
+ source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
+
+2021-05-11 Nick Clifton <nickc@redhat.com>
+
+ PR 27840
+ * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
+ the end of the code buffer.
+
+2021-05-06 Stafford Horne <shorne@gmail.com>
+
+ PR 21464
+ * or1k-asm.c: Regenerate.
+
+2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
+
+ * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
+ info->insn_info_valid.
+
+2021-04-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (lea): Add Optimize.
+ * opcodes/i386-tbl.h: Re-generate.
+
+2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
+
+ * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
+ of l32r fetch and display referenced literal value.
+
+2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
+
+ * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
+ to 4 for literal disassembly.
+
+2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
+ for TLBI instruction.
+
+2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
+ DC instruction.
+
+2021-04-19 Jan Beulich <jbeulich@suse.com>
+
+ * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
+ "qualifier".
+ (convert_mov_to_movewide): Add initializer for "value".
+
+2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add RME system registers.
+
+2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
+
+ * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
+ "addi d,CV,z" to "c.mv d,CV".
+
+2021-04-12 Alan Modra <amodra@gmail.com>
+
+ * configure.ac (--enable-checking): Add support.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+
+2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
+
+ * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
+ LD64/ST64 instructions to lse_atomic instead of ldstexcl.
+
+2021-04-09 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (struct dis_private): Add "special".
+ (POWERPC_DIALECT): Delete. Replace uses with..
+ (private_data): ..this. New inline function.
+ (disassemble_init_powerpc): Init "special" names.
+ (skip_optional_operands): Add is_pcrel arg, set when detecting R
+ field of prefix instructions.
+ (bsearch_reloc, print_got_plt): New functions.
+ (print_insn_powerpc): For pcrel instructions, print target address
+ and symbol if known, and decode plt and got loads too.
+
+2021-04-08 Alan Modra <amodra@gmail.com>
+
+ PR 27684
+ * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
+
+2021-04-08 Alan Modra <amodra@gmail.com>
+
+ PR 27676
+ * ppc-opc.c (DCBT_EO): Move earlier.
+ (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
+ (powerpc_operands): Add THCT and THDS entries.
+ (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
+
+2021-04-06 Alan Modra <amodra@gmail.com>
+
+ * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
+ * s12z-dis.c (decode_possible_symbol): Use symbol returned from
+ symbol_at_address_func.
+
+2021-04-05 Alan Modra <amodra@gmail.com>
+
+ * configure.ac: Don't check for limits.h, string.h, strings.h or
+ stdlib.h.
+ (AC_ISC_POSIX): Don't invoke.
+ * sysdep.h: Include stdlib.h and string.h unconditionally.
+ * i386-opc.h: Include limits.h unconditionally.
+ * wasm32-dis.c: Likewise.
+ * cgen-opc.c: Don't include alloca-conf.h.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+
+2021-04-01 Martin Liska <mliska@suse.cz>
+
+ * arm-dis.c (strneq): Remove strneq and use startswith.
+ * cr16-dis.c (print_insn_cr16): Likewise.
+ * score-dis.c (streq): Likewise.
+ (strneq): Likewise.
+ * score7-dis.c (strneq): Likewise.
+
+2021-04-01 Alan Modra <amodra@gmail.com>
+
+ PR 27675
+ * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
+
+2021-03-31 Alan Modra <amodra@gmail.com>
+
+ * sysdep.h (POISON_BFD_BOOLEAN): Define.
+ * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
+ * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
+ * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
+ * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
+ * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
+ * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
+ * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
+ * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
+ * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
+ * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
+ * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
+ * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
+ * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
+ and TRUE with true throughout.
+
+2021-03-31 Alan Modra <amodra@gmail.com>
+
+ * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
+ * aarch64-dis.h: Likewise.
+ * aarch64-opc.c: Likewise.
+ * avr-dis.c: Likewise.
+ * csky-dis.c: Likewise.
+ * nds32-asm.c: Likewise.
+ * nds32-dis.c: Likewise.
+ * nfp-dis.c: Likewise.
+ * riscv-dis.c: Likewise.
+ * s12z-dis.c: Likewise.
+ * wasm32-dis.c: Likewise.
+
+2021-03-30 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
+ (i386_seg_prefixes): New.
+ * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
+ (i386_seg_prefixes): Declare.
+
+2021-03-30 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
+
+2021-03-30 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
+ * i386-reg.tbl (st): Move down.
+ (st(0)): Delete. Extend comment.
+ * i386-tbl.h: Re-generate.
+
+2021-03-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
+ (cmpsd): Move next to cmps.
+ (movsd): Move next to movs.
+ (cmpxchg16b): Move to separate section.
+ (fisttp, fisttpll): Likewise.
+ (monitor, mwait): Likewise.
+ * i386-tbl.h: Re-generate.
+
+2021-03-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (psadbw): Add <sse2:comm>.
+ (vpsadbw): Add C.
+ * i386-tbl.h: Re-generate.
+
+2021-03-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
+ pclmul, gfni): New templates. Use them wherever possible. Move
+ SSE4.1 pextrw into respective section.
+ * i386-tbl.h: Re-generate.
+
+2021-03-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
+ strtoull(). Bump upper loop bound. Widen masks. Sanity check
+ "length".
+ * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
+ Convert all of their uses to representation in opcode.
+
+2021-03-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (struct insn_template): Shrink base_opcode to 16
+ bits. Shrink extension_opcode to 9 bits. Make it signed. Change
+ value of None. Shrink operands to 3 bits.
+
+2021-03-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (process_i386_opcode_modifier): New parameter
+ "space".
+ (output_i386_opcode): New local variable "space". Adjust
+ process_i386_opcode_modifier() invocation.
+ (process_i386_opcodes): Adjust process_i386_opcode_modifier()
+ invocation.
+ * i386-tbl.h: Re-generate.
+
+2021-03-29 Alan Modra <amodra@gmail.com>
+
+ * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
+ (fp_qualifier_p, get_data_pattern): Likewise.
+ (aarch64_get_operand_modifier_from_value): Likewise.
+ (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
+ (operand_variant_qualifier_p): Likewise.
+ (qualifier_value_in_range_constraint_p): Likewise.
+ (aarch64_get_qualifier_esize): Likewise.
+ (aarch64_get_qualifier_nelem): Likewise.
+ (aarch64_get_qualifier_standard_value): Likewise.
+ (get_lower_bound, get_upper_bound): Likewise.
+ (aarch64_find_best_match, match_operands_qualifier): Likewise.
+ (aarch64_print_operand): Likewise.
+ * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
+ (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
+ (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
+ * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
+ * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
+ (print_insn_tic6x): Likewise.
+
+2021-03-29 Alan Modra <amodra@gmail.com>
+
+ * arc-dis.c (extract_operand_value): Correct NULL cast.
+ * frv-opc.h: Regenerate.
+
+2021-03-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
+ MMX form.
+ * i386-tbl.h: Re-generate.
+
+2021-03-25 Abid Qadeer <abidh@codesourcery.com>
+
+ * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
+ immediate in br.n instruction.
+
+2021-03-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (XMGatherD, VexGatherD): New.
+ (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
+ (print_insn): Check masking for S/G insns.
+ (OP_E_memory): New local variable check_gather. Extend mandatory
+ SIB check. Check register conflicts for (EVEX-encoded) gathers.
+ Extend check for disallowed 16-bit addressing.
+ (OP_VEX): New local variables modrm_reg and sib_index. Convert
+ if()s to switch(). Check register conflicts for (VEX-encoded)
+ gathers. Drop no longer reachable cases.
+ * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
+ vgatherdp*.
+
2021-03-25 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
projects / binutils-gdb.git / blobdiff