+2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * arm-dis.c (neon_opcodes): Adjust print string for vshll.
+
+2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
+
+ * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
+ +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
+ +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
+ (MSA): New define.
+ (MSA64): New define.
+ (micromips_opcodes): Add MSA instructions.
+ * mips-dis.c (msa_control_names): New array.
+ (mips_abi_choice): Add ASE_MSA to mips32r2.
+ Remove ASE_MDMX from mips64r2.
+ Add ASE_MSA and ASE_MSA64 to mips64r2.
+ (parse_mips_dis_option): Handle -Mmsa.
+ (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
+ (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
+ (print_mips_disassembler_options): Print -Mmsa.
+ * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
+ +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
+ (MSA): New define.
+ (MSA64): New define.
+ (mips_builtin_op): Add MSA instructions.
+
+2013-10-13 Sandra Loosemore <sandra@codesourcery.com>
+
+ * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
+ as the primary name of r30.
+
+2013-10-12 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
+ default case.
+ (OP_E_register): Move v_bnd_mode alongside m_mode.
+ * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
+ Drop Reg16 and Disp16. Add NoRex64.
+ (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
+ * i386-tbl.h: Re-generate.
+
+2013-10-10 Sean Keys <skeys@ipdatasys.com>
+
+ * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
+ table.
+ * xgate-dis.c (print_insn): Refactor to work with table change.
+
+2013-10-10 Roland McGrath <mcgrathr@google.com>
+
+ * i386-dis.c (oappend_maybe_intel): New function.
+ (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
+ (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
+ (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
+
+ * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
+ possible compiler warnings when the union's initializer is
+ actually meant for the 'preg' enum typed member.
+ * crx-opc.c (REG): Likewise.
+
+ * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
+ Remove duplicate const qualifier.
+
+2013-10-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
+ (clflush): Use Anysize instead of Byte|Unspecified.
+ (prefetch*): Likewise.
+ * i386-tbl.h: Re-generate.
+
+2013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
+
+ * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
+
+2013-09-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
+ * i386-init.h: Regenerated.
+
+2013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
+
+ * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
+ * i386-init.h: Regenerated.
+
+2013-09-20 Alan Modra <amodra@gmail.com>
+
+ * configure: Regenerate.
+
+2013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
+
+ * s390-opc.txt (clih): Make the immediate unsigned.
+
+2013-09-04 Roland McGrath <mcgrathr@google.com>
+
+ PR gas/15914
+ * arm-dis.c (arm_opcodes): Add udf.
+ (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
+ (thumb32_opcodes): Add udf.w.
+ (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
+
+2013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
+ For the load fp integer instructions only the suppression flag was
+ new with z196 version.
+
+2013-08-28 Nick Clifton <nickc@redhat.com>
+
+ * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
+ immediate is not suitable for the 32-bit ABI.
+
+2013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
+ replacing NODS.
+
+2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
+
+ PR binutils/15834
+ * aarch64-asm.c: Fix typos.
+ * aarch64-dis.c: Likewise.
+ * msp430-dis.c: Likewise.
+
+2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
+ macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
+ Use +H rather than +C for the real "dext".
+ * mips-opc.c (mips_builtin_opcodes): Likewise.
+
+2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
+ * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
+ and OPTIONAL_MAPPED_REG.
+ * mips-opc.c (decode_mips_operand): Likewise.
+ * mips16-opc.c (decode_mips16_operand): Likewise.
+ * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
+
+2013-08-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
+ (PREFIX_EVEX_0F3A3F): Likewise.
+ * i386-dis-evex.h (evex_table): Updated.
+
+2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
+ VCLIPW.
+
+2013-08-05 Eric Botcazou <ebotcazou@adacore.com>
+ Konrad Eisele <konrad@gaisler.com>
+
+ * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
+ bfd_mach_sparc.
+ * sparc-opc.c (MASK_LEON): Define.
+ (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
+ (letandleon): New macro.
+ (v9andleon): Likewise.
+ (sparc_opc): Add leon.
+ (umac): Enable for letandleon.
+ (smac): Likewise.
+ (casa): Enable for v9andleon.
+ (cas): Likewise.
+ (casl): Likewise.
+
+2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
+ Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
+ OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
+ (print_vu0_channel): New function.
+ (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
+ (print_insn_args): Handle '#'.
+ (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
+ * mips-opc.c (mips_vu0_channel_mask): New constant.
+ (decode_mips_operand): Handle new VU0 operand types.
+ (VU0, VU0CH): New macros.
+ (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
+ for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
+ Use "+6" rather than "G" for QMFC2 and QMTC2.
+
+2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-formats.h (PCREL): Reorder parameters and update the definition
+ to match new mips_pcrel_operand layout.
+ (JUMP, JALX, BRANCH): Update accordingly.
+ * mips16-opc.c (decode_mips16_operand): Likewise.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * micromips-opc.c (WR_s): Delete.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
+ New macros.
+ (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
+ (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
+ (mips_builtin_opcodes): Use the new position-based read-write flags
+ instead of field-based ones. Use UDI for "udi..." instructions.
+ * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
+ New macros.
+ (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
+ (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
+ (WR_SP, RD_16): New macros.
+ (RD_SP): Redefine as an INSN2_* flag.
+ (MOD_SP): Redefine in terms of RD_SP and WR_SP.
+ (mips16_opcodes): Use the new position-based read-write flags
+ instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
+ pinfo2 field.
+ * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
+ New macros.
+ (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
+ (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
+ (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
+ (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
+ (micromips_opcodes): Use the new position-based read-write flags
+ instead of field-based ones.
+ * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
+ (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
+ of field-based flags.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
+ (WR_SP): Replace with...
+ (MOD_SP): ...this.
+ (mips16_opcodes): Update accordingly.
+ * mips-dis.c (print_insn_mips16): Likewise.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips16-opc.c (mips16_opcodes): Reformat.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
+ for operands that are hard-coded to $0.
+ * micromips-opc.c (micromips_opcodes): Likewise.
+
2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
* mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
projects / binutils-gdb.git / blobdiff