+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
+ TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
+
+2020-09-26 Alan Modra <amodra@gmail.com>
+
+ * csky-opc.h: Formatting.
+ (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
+ (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
+ and shift 1u.
+ (get_register_number): Likewise.
+ * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
+
+2020-09-24 Lili Cui <lili.cui@intel.com>
+
+ PR 26654
+ * i386-dis.c (enum): Put MOD_VEX_0F38* together.
+
+2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * csky-dis.c (csky_output_operand): Enclose body of if in curly
+ braces.
+
+2020-09-24 Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
+ PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
+ X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
+ X86_64_0F01_REG_1_RM_7_P_2.
+ (prefix_table): Likewise.
+ (x86_64_table): Likewise.
+ (rm_table): Likewise.
+ * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
+ and CPU_ANY_TDX_FLAGS.
+ (cpu_flags): Add CpuTDX.
+ * i386-opc.h (enum): Add CpuTDX.
+ (i386_cpu_flags): Add cputdx.
+ * i386-opc.tbl: Add TDX insns.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
+
+ * csky-dis.c (using_abi): New.
+ (parse_csky_dis_options): New function.
+ (get_gr_name): New function.
+ (get_cr_name): New function.
+ (csky_output_operand): Use get_gr_name and get_cr_name to
+ disassemble and add handle of OPRND_TYPE_IMM5b_LS.
+ (print_insn_csky): Parse disassembler options.
+ * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
+ (GENARAL_REG_BANK): Define.
+ (REG_SUPPORT_ALL): Define.
+ (REG_SUPPORT_ALL): New.
+ (ASH): Define.
+ (REG_SUPPORT_A): Define.
+ (REG_SUPPORT_B): Define.
+ (REG_SUPPORT_C): Define.
+ (REG_SUPPORT_D): Define.
+ (REG_SUPPORT_E): Define.
+ (csky_abiv1_general_regs): New.
+ (csky_abiv1_control_regs): New.
+ (csky_abiv2_general_regs): New.
+ (csky_abiv2_control_regs): New.
+ (get_register_name): New function.
+ (get_register_number): New function.
+ (csky_get_general_reg_name): New function.
+ (csky_get_general_regno): New function.
+ (csky_get_control_reg_name): New function.
+ (csky_get_control_regno): New function.
+ (csky_v2_opcodes): Prefer two oprerans format for bclri and
+ bseti, strengthen the operands legality check of addc, zext
+ and sext.
+
+2020-09-23 Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
+ MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
+ MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
+ MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
+ PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
+ (reg_table): New instructions (see prefixes above).
+ (prefix_table): Likewise.
+ (three_byte_table): Likewise.
+ (mod_table): Likewise
+ * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
+ CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
+ (cpu_flags): Likewise.
+ (operand_type_init): Likewise.
+ * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
+ (i386_cpu_flags): Add cpukl and cpuwide_kl.
+ * i386-opc.tbl: Add KL and WIDE_KL insns.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2020-09-21 Alan Modra <amodra@gmail.com>
+
+ * rx-dis.c (flag_names): Add missing comma.
+ (register_names, flag_names, double_register_names),
+ (double_register_high_names, double_register_low_names),
+ (double_control_register_names, double_condition_names): Remove
+ trailing commas.
+
+2020-09-18 David Faust <david.faust@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-desc.h: Likewise.
+ * bpf-opc.c: Likewise.
+ * bpf-opc.h: Likewise.
+
+2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * csky-dis.c (csky_get_disassembler): Don't return NULL when there
+ is no BFD.
+
+2020-09-16 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
+
+2020-09-10 Nick Clifton <nickc@redhat.com>
+
+ * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
+ for hidden, local, no-type symbols.
+ (disassemble_init_powerpc): Point the symbol_is_valid field in the
+ info structure at the new function.
+
+2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
+ * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
+ opcode fixing.
+
+2020-09-10 Nick Clifton <nickc@redhat.com>
+
+ * csky-dis.c (csky_output_operand): Coerce the immediate values to
+ long before printing.
+
+2020-09-10 Alan Modra <amodra@gmail.com>
+
+ * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
+
+2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
+ ISA flag.
+
+2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-dis.c (csky_output_operand): Add handlers for
+ OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
+ OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
+ to support FPUV3 instructions.
+ * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
+ OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
+ OPRND_TYPE_DFLOAT_FMOVI.
+ (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
+ OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
+ OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
+ OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
+ OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
+ OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
+ OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
+ OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
+ OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
+ OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
+ OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
+ OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
+ OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
+ (csky_v2_opcodes): Add FPUV3 instructions.
+
+2020-09-08 Alex Coplan <alex.coplan@arm.com>
+
+ * aarch64-dis.c (print_operands): Pass CPU features to
+ aarch64_print_operand().
+ * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
+ preferred disassembly of system registers.
+ (SR_RNG): Refactor to use new SR_FEAT2 macro.
+ (SR_FEAT2): New.
+ (SR_V8_1_A): New.
+ (SR_V8_4_A): New.
+ (SR_V8_A): New.
+ (SR_V8_R): New.
+ (SR_EXPAND_ELx): New.
+ (SR_EXPAND_EL12): New.
+ (aarch64_sys_regs): Specify which registers are only on
+ A-profile, add R-profile system registers.
+ (ENC_BARLAR): New.
+ (PRBARn_ELx): New.
+ (PRLARn_ELx): New.
+ (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
+ Armv8-R AArch64.
+
+2020-09-08 Alex Coplan <alex.coplan@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_v8_r): New.
+ (ARMV8_R): New.
+ (V8_R_INSN): New.
+ (aarch64_opcode_table): Add dfb.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+
+2020-09-08 Alex Coplan <alex.coplan@arm.com>
+
+ * aarch64-dis.c (arch_variant): New.
+ (determine_disassembling_preference): Disassemble according to
+ arch variant.
+ (select_aarch64_variant): New.
+ (print_insn_aarch64): Set feature set.
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
+ (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
+ (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
+ (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
+ (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
+ (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
+ (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
+ for value parameter and update code to suit.
+ (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
+ (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * i386-dis.c (OP_E_memory): Don't cast to signed type when
+ negating.
+ (get32, get32s): Use unsigned types in shift expressions.
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * csky-dis.c (print_insn_csky): Use unsigned type for "given".
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * crx-dis.c: Whitespace.
+ (print_arg): Use unsigned type for longdisp and mask variables,
+ and for left shift constant.
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
+ * bpf-ibld.c: Regenerate.
+ * epiphany-ibld.c: Regenerate.
+ * fr30-ibld.c: Regenerate.
+ * frv-ibld.c: Regenerate.
+ * ip2k-ibld.c: Regenerate.
+ * iq2000-ibld.c: Regenerate.
+ * lm32-ibld.c: Regenerate.
+ * m32c-ibld.c: Regenerate.
+ * m32r-ibld.c: Regenerate.
+ * mep-ibld.c: Regenerate.
+ * mt-ibld.c: Regenerate.
+ * or1k-ibld.c: Regenerate.
+ * xc16x-ibld.c: Regenerate.
+ * xstormy16-ibld.c: Regenerate.
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * bfin-dis.c (MASKBITS): Use SIGNBIT.
+
+2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Move divul and divsl
+ to CSKYV2_ISA_3E3R3 instruction set.
+
+2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
+
+2020-09-01 Alan Modra <amodra@gmail.com>
+
+ * mep-ibld.c: Regenerate.
+
+2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-dis.c (csky_output_operand): Assign dis_info.value for
+ OPRND_TYPE_VREG.
+
+2020-08-30 Alan Modra <amodra@gmail.com>
+
+ * cr16-dis.c: Formatting.
+ (parameter): Delete struct typedef. Use dwordU instead
+ throughout file.
+ (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
+ and tbitb.
+ (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
+
+2020-08-29 Alan Modra <amodra@gmail.com>
+
+ PR 26446
+ * csky-opc.h (MAX_OPRND_NUM): Define to 5.
+ (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
+
+2020-08-28 Alan Modra <amodra@gmail.com>
+
+ PR 26449
+ PR 26450
+ * cgen-ibld.in (insert_1): Use 1UL in forming mask.
+ (extract_normal): Likewise.
+ (insert_normal): Likewise, and move past zero length test.
+ (put_insn_int_value): Handle mask for zero length, use 1UL.
+ * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
+ * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
+ * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
+ * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
+
+2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-dis.c (CSKY_DEFAULT_ISA): Define.
+ (csky_dis_info): Add member isa.
+ (csky_find_inst_info): Skip instructions that do not belong to
+ current CPU.
+ (csky_get_disassembler): Get infomation from attribute section.
+ (print_insn_csky): Set defualt ISA flag.
+ * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
+ * csky-opc.h (struct csky_opcode): Change isa_flag16 and
+ isa_flag32'type to unsigned 64 bits.
+
+2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
+
+ * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
+
+2020-08-26 David Faust <david.faust@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-desc.h: Likewise.
+ * bpf-opc.c: Likewise.
+ * bpf-opc.h: Likewise.
+ * disassemble.c (disassemble_init_for_target): Set bits for xBPF
+ ISA when appropriate.
+
+2020-08-25 Alan Modra <amodra@gmail.com>
+
+ PR 26504
+ * vax-dis.c (parse_disassembler_options): Always add at least one
+ to entry_addr_total_slots.
+
+2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
+ in other CPUs to speed up disassembling.
+ * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
+ Change plsli.u16 to plsli.16, change sync's operand format.
+
+2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
+
+2020-08-21 Nick Clifton <nickc@redhat.com>
+
+ * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
+ symbols.
+
2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
* csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
- respectively.
+ respectively.
(dis386_twobyte, three_byte_table, vex_table, vex_len_table,
vex_w_table, mod_table): Replace / remove respective entries.
(print_insn): Move up dp->prefix_requirement handling. Handle
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
- * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
+ * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
(neon_opcodes): Likewise.
(select_arm_features): Make sure we enable MVE bits when selecting
armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
* i386-dis.c (print_insn): Initialize the insn info fields, and
detect jumps.
-2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
+2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
* arc-opc.c (C_NE): Make it required.
-2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
+2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
- * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
+ * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
reserved register name.
2020-01-13 Alan Modra <amodra@gmail.com>
* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
uzip{1,2}.
- * opcodes/aarch64-dis-2.c: Re-generate.
+ * aarch64-dis-2.c: Re-generate.
2020-01-03 Jan Beulich <jbeulich@suse.com>
* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
FMMLA encoding.
- * opcodes/aarch64-dis-2.c: Re-generate.
+ * aarch64-dis-2.c: Re-generate.
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>