+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
+ TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
+
+2020-09-26 Alan Modra <amodra@gmail.com>
+
+ * csky-opc.h: Formatting.
+ (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
+ (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
+ and shift 1u.
+ (get_register_number): Likewise.
+ * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
+
+2020-09-24 Lili Cui <lili.cui@intel.com>
+
+ PR 26654
+ * i386-dis.c (enum): Put MOD_VEX_0F38* together.
+
+2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * csky-dis.c (csky_output_operand): Enclose body of if in curly
+ braces.
+
+2020-09-24 Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
+ PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
+ X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
+ X86_64_0F01_REG_1_RM_7_P_2.
+ (prefix_table): Likewise.
+ (x86_64_table): Likewise.
+ (rm_table): Likewise.
+ * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
+ and CPU_ANY_TDX_FLAGS.
+ (cpu_flags): Add CpuTDX.
+ * i386-opc.h (enum): Add CpuTDX.
+ (i386_cpu_flags): Add cputdx.
+ * i386-opc.tbl: Add TDX insns.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
+
+ * csky-dis.c (using_abi): New.
+ (parse_csky_dis_options): New function.
+ (get_gr_name): New function.
+ (get_cr_name): New function.
+ (csky_output_operand): Use get_gr_name and get_cr_name to
+ disassemble and add handle of OPRND_TYPE_IMM5b_LS.
+ (print_insn_csky): Parse disassembler options.
+ * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
+ (GENARAL_REG_BANK): Define.
+ (REG_SUPPORT_ALL): Define.
+ (REG_SUPPORT_ALL): New.
+ (ASH): Define.
+ (REG_SUPPORT_A): Define.
+ (REG_SUPPORT_B): Define.
+ (REG_SUPPORT_C): Define.
+ (REG_SUPPORT_D): Define.
+ (REG_SUPPORT_E): Define.
+ (csky_abiv1_general_regs): New.
+ (csky_abiv1_control_regs): New.
+ (csky_abiv2_general_regs): New.
+ (csky_abiv2_control_regs): New.
+ (get_register_name): New function.
+ (get_register_number): New function.
+ (csky_get_general_reg_name): New function.
+ (csky_get_general_regno): New function.
+ (csky_get_control_reg_name): New function.
+ (csky_get_control_regno): New function.
+ (csky_v2_opcodes): Prefer two oprerans format for bclri and
+ bseti, strengthen the operands legality check of addc, zext
+ and sext.
+
+2020-09-23 Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
+ MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
+ MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
+ MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
+ PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
+ (reg_table): New instructions (see prefixes above).
+ (prefix_table): Likewise.
+ (three_byte_table): Likewise.
+ (mod_table): Likewise
+ * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
+ CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
+ (cpu_flags): Likewise.
+ (operand_type_init): Likewise.
+ * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
+ (i386_cpu_flags): Add cpukl and cpuwide_kl.
+ * i386-opc.tbl: Add KL and WIDE_KL insns.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2020-09-21 Alan Modra <amodra@gmail.com>
+
+ * rx-dis.c (flag_names): Add missing comma.
+ (register_names, flag_names, double_register_names),
+ (double_register_high_names, double_register_low_names),
+ (double_control_register_names, double_condition_names): Remove
+ trailing commas.
+
+2020-09-18 David Faust <david.faust@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-desc.h: Likewise.
+ * bpf-opc.c: Likewise.
+ * bpf-opc.h: Likewise.
+
+2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * csky-dis.c (csky_get_disassembler): Don't return NULL when there
+ is no BFD.
+
+2020-09-16 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
+
2020-09-10 Nick Clifton <nickc@redhat.com>
* ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
- respectively.
+ respectively.
(dis386_twobyte, three_byte_table, vex_table, vex_len_table,
vex_w_table, mod_table): Replace / remove respective entries.
(print_insn): Move up dp->prefix_requirement handling. Handle
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
- * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
+ * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
(neon_opcodes): Likewise.
(select_arm_features): Make sure we enable MVE bits when selecting
armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
* i386-dis.c (print_insn): Initialize the insn info fields, and
detect jumps.
-2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
+2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
* arc-opc.c (C_NE): Make it required.
-2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
+2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
- * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
+ * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
reserved register name.
2020-01-13 Alan Modra <amodra@gmail.com>
* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
uzip{1,2}.
- * opcodes/aarch64-dis-2.c: Re-generate.
+ * aarch64-dis-2.c: Re-generate.
2020-01-03 Jan Beulich <jbeulich@suse.com>
* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
FMMLA encoding.
- * opcodes/aarch64-dis-2.c: Re-generate.
+ * aarch64-dis-2.c: Re-generate.
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
projects / binutils-gdb.git / blobdiff