m68k bfd.h tidy

[binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 97c29429299908e964b71c5385d4ddc07f6cb5f0..ef50402da85a7d21431258e636a6e28b9c8d3e80 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,82 @@
+2019-09-23  Alan Modra  <amodra@gmail.com>
+
+       * m68k-dis.c: Include cpu-m68k.h
+
+2019-09-23  Alan Modra  <amodra@gmail.com>
+
+       * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
+       "elf/mips.h" earlier.
+
+2018-09-20  Jan Beulich  <jbeulich@suse.com>
+
+       PR gas/25012
+       * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
+       with SReg operand.
+       * i386-tbl.h: Re-generate.
+
+2019-09-18  Alan Modra  <amodra@gmail.com>
+
+       * arc-ext.c: Update throughout for bfd section macro changes.
+
+2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
+
+       * Makefile.in: Re-generate.
+       * configure: Re-generate.
+
+2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
+
+       * riscv-opc.c (riscv_opcodes): Change subset field
+       to insn_class field for all instructions.
+       (riscv_insn_types): Likewise.
+
+2019-09-16  Phil Blundell  <pb@pbcl.net>
+
+       * configure: Regenerated.
+
+2019-09-10  Miod Vallat  <miod@online.fr>
+
+       PR 24982
+       * m68k-opc.c: Correct aliases for tdivsl and tdivul.
+
+2019-09-09  Phil Blundell  <pb@pbcl.net>
+
+       binutils 2.33 branch created.
+
+2019-09-03  Nick Clifton  <nickc@redhat.com>
+
+       PR 24961
+       * tic30-dis.c (get_indirect_operand): Check for bufcnt being
+       greater than zero before indexing via (bufcnt -1).
+
+2019-09-03  Nick Clifton  <nickc@redhat.com>
+
+       PR 24958
+       * mmix-dis.c (MAX_REG_NAME_LEN): Define.
+       (MAX_SPEC_REG_NAME_LEN): Define.
+       (struct mmix_dis_info): Use defined constants for array lengths.
+       (get_reg_name): New function.
+       (get_sprec_reg_name): New function.
+       (print_insn_mmix): Use new functions.
+
+2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
+
+       * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
+       (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
+       (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
+
+2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
+       tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
+       (aarch64_sys_reg_supported_p): Update checks for the above.
+
+2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
+
+       * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
+       cases MVE_SQRSHRL and MVE_UQRSHLL.
+       (print_insn_mve): Add case for specifier 'k' to check
+       specific bit of the instruction.
+
 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 
        PR 24854