+2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Replace S with Load.
+ * i386-opc.h (S): Removed.
+ (Load): New.
+ (i386_opcode_modifier): Replace s with load.
+ * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
+ and {evex}. Replace S with Load.
+ * i386-tbl.h: Regenerated.
+
+2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Use CpuCET on rdsspq.
+ * i386-tbl.h: Regenerated.
+
+2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
+ <vsx>: Do not use PPC_OPCODE_VSX3;
+
+2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
+
+2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (REG_0F1E_MOD_3): New enum.
+ (MOD_0F1E_PREFIX_1): Likewise.
+ (MOD_0F38F5_PREFIX_2): Likewise.
+ (MOD_0F38F6_PREFIX_0): Likewise.
+ (RM_0F1E_MOD_3_REG_7): Likewise.
+ (PREFIX_MOD_0_0F01_REG_5): Likewise.
+ (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
+ (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
+ (PREFIX_0F1E): Likewise.
+ (PREFIX_MOD_0_0FAE_REG_5): Likewise.
+ (PREFIX_0F38F5): Likewise.
+ (dis386_twobyte): Use PREFIX_0F1E.
+ (reg_table): Add REG_0F1E_MOD_3.
+ (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
+ PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
+ PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
+ PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
+ (three_byte_table): Use PREFIX_0F38F5.
+ (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
+ Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
+ (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
+ RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
+ PREFIX_MOD_3_0F01_REG_5_RM_2.
+ * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
+ (cpu_flags): Add CpuCET.
+ * i386-opc.h (CpuCET): New enum.
+ (CpuUnused): Commented out.
+ (i386_cpu_flags): Add cpucet.
+ * i386-opc.tbl: Add Intel CET instructions.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2017-03-06 Alan Modra <amodra@gmail.com>
+
+ PR 21124
+ * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
+ (extract_raq, extract_ras, extract_rbx): New functions.
+ (powerpc_operands): Use opposite corresponding insert function.
+ (Q_MASK): Define.
+ (powerpc_opcodes): Apply Q_MASK to all quad insns with even
+ register restriction.
+
+2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
+
+ * disassemble.c Include "safe-ctype.h".
+ (disassemble_init_for_target): Handle s390 init.
+ (remove_whitespace_and_extra_commas): New function.
+ (disassembler_options_cmp): Likewise.
+ * arm-dis.c: Include "libiberty.h".
+ (NUM_ELEM): Delete.
+ (regnames): Use long disassembler style names.
+ Add force-thumb and no-force-thumb options.
+ (NUM_ARM_REGNAMES): Rename from this...
+ (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
+ (get_arm_regname_num_options): Delete.
+ (set_arm_regname_option): Likewise.
+ (get_arm_regnames): Likewise.
+ (parse_disassembler_options): Likewise.
+ (parse_arm_disassembler_option): Rename from this...
+ (parse_arm_disassembler_options): ...to this. Make static.
+ Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
+ (print_insn): Use parse_arm_disassembler_options.
+ (disassembler_options_arm): New function.
+ (print_arm_disassembler_options): Handle updated regnames.
+ * ppc-dis.c: Include "libiberty.h".
+ (ppc_opts): Add "32" and "64" entries.
+ (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
+ (powerpc_init_dialect): Add break to switch statement.
+ Use new FOR_EACH_DISASSEMBLER_OPTION macro.
+ (disassembler_options_powerpc): New function.
+ (print_ppc_disassembler_options): Use ARRAY_SIZE.
+ Remove printing of "32" and "64".
+ * s390-dis.c: Include "libiberty.h".
+ (init_flag): Remove unneeded variable.
+ (struct s390_options_t): New structure type.
+ (options): New structure.
+ (init_disasm): Rename from this...
+ (disassemble_init_s390): ...to this. Add initializations for
+ current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
+ (print_insn_s390): Delete call to init_disasm.
+ (disassembler_options_s390): New function.
+ (print_s390_disassembler_options): Print using information from
+ struct 'options'.
+ * po/opcodes.pot: Regenerate.
+
+2017-02-28 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (PCMPESTR_Fixup): New.
+ (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
+ (prefix_table): Use PCMPESTR_Fixup.
+ (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
+ PCMPESTR_Fixup.
+ (vex_w_table): Delete VPCMPESTR{I,M} entries.
+ * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
+ Split 64-bit and non-64-bit variants.
+ * opcodes/i386-tbl.h: Re-generate.
+
+2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
+ (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
+ (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
+ (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
+ (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
+ (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
+ (OP_SVE_V_HSD): New macros.
+ (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
+ (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
+ (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
+ (aarch64_opcode_table): Add new SVE instructions.
+ (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
+ for rotation operands. Add new SVE operands.
+ * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
+ (ins_sve_quad_index): Likewise.
+ (ins_imm_rotate): Split into...
+ (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
+ * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
+ (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
+ functions.
+ (aarch64_ins_sve_addr_ri_s4): New function.
+ (aarch64_ins_sve_quad_index): Likewise.
+ (do_misc_encoding): Handle "MOV Zn.Q, Qm".
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
+ (ext_sve_quad_index): Likewise.
+ (ext_imm_rotate): Split into...
+ (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
+ * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
+ (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
+ functions.
+ (aarch64_ext_sve_addr_ri_s4): New function.
+ (aarch64_ext_sve_quad_index): Likewise.
+ (aarch64_ext_sve_index): Allow quad indices.
+ (do_misc_decoding): Likewise.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
+ aarch64_field_kinds.
+ (OPD_F_OD_MASK): Widen by one bit.
+ (OPD_F_NO_ZR): Bump accordingly.
+ (get_operand_field_width): New function.
+ * aarch64-opc.c (fields): Add new SVE fields.
+ (operand_general_constraint_met_p): Handle new SVE operands.
+ (aarch64_print_operand): Likewise.
+ * aarch64-opc-2.c: Regenerate.
+
+2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
+ (aarch64_feature_compnum): ...this.
+ (SIMD_V8_3): Replace with...
+ (COMPNUM): ...this.
+ (CNUM_INSN): New macro.
+ (aarch64_opcode_table): Use it for the complex number instructions.
+
+2017-02-24 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
+
+2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
+
+ Add support for associating SPARC ASIs with an architecture level.
+ * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
+ * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
+ decoding of SPARC ASIs.
+
+2017-02-23 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
+ 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
+
+2017-02-21 Jan Beulich <jbeulich@suse.com>
+
+ * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
+ 1 (instead of to itself). Correct typo.
+
+2017-02-14 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
+ pseudoinstructions.
+
+2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
+ (aarch64_sys_reg_supported_p): Handle them.
+
+2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-opc.c (UIMM6_20R): Define.
+ (SIMM12_20): Use above.
+ (SIMM12_20R): Define.
+ (SIMM3_5_S): Use above.
+ (UIMM7_A32_11R_S): Define.
+ (UIMM7_9_S): Use above.
+ (UIMM3_13R_S): Define.
+ (SIMM11_A32_7_S): Use above.
+ (SIMM9_8R): Define.
+ (UIMM10_A32_8_S): Use above.
+ (UIMM8_8R_S): Define.
+ (W6): Use above.
+ (arc_relax_opcodes): Use all above defines.
+
+2017-02-15 Vineet Gupta <vgupta@synopsys.com>
+
+ * arc-regs.h: Distinguish some of the registers different on
+ ARC700 and HS38 cpus.
+
+2017-02-14 Alan Modra <amodra@gmail.com>
+
+ PR 21118
+ * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
+ with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
+
+2017-02-11 Stafford Horne <shorne@gmail.com>
+ Alan Modra <amodra@gmail.com>
+
+ * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
+ Use insn_bytes_value and insn_int_value directly instead. Don't
+ free allocated memory until function exit.
+
+2017-02-10 Nicholas Piggin <npiggin@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
+
2017-02-03 Nick Clifton <nickc@redhat.com>
PR 21096
projects / binutils-gdb.git / blobdiff