+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
+ (decode_pseudoOChar_0): New function.
+ (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
+
+2010-09-22 Robin Getz <robin.getz@analog.com>
+
+ * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
+ LSHIFT instead of SHIFT.
+
+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (constant_formats): Constify the whole structure.
+ (fmtconst): Add const to return value.
+ (reg_names): Mark const.
+ (decode_multfunc): Mark s0/s1 as const.
+ (decode_macfunc): Mark a/sop as const.
+
+2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
+
+ * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
+
+2010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
+ "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
+
+2010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
+
+ * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
+ dlx_insn_type array.
+
+2010-08-31 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/11960
+ * i386-dis.c (sIv): New.
+ (dis386): Replace Iq with sIv on "pushT".
+ (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
+ (x86_64_table): Replace {T|}/{P|} with P.
+ (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
+ (OP_sI): Update v_mode. Remove w_mode.
+
+2010-08-27 Nathan Froyd <froydnj@codesourcery.com>
+
+ * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
+ on E500 and E500MC.
+
+2010-08-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
+ prefetchw.
+
+2010-08-06 Quentin Neill <quentin.neill@amd.com>
+
+ * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
+ to processor flags for PENTIUMPRO processors and later.
+ * i386-opc.h (enum): Add CpuNop.
+ (i386_cpu_flags): Add cpunop bit.
+ * i386-opc.tbl: Change nop cpu_flags.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2010-08-06 Quentin Neill <quentin.neill@amd.com>
+
+ * i386-opc.h (enum): Fix typos in comments.
+
+2010-08-06 Alan Modra <amodra@gmail.com>
+
+ * disassemble.c: Formatting.
+ (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
+
+2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
+ * i386-tbl.h: Regenerated.
+
+2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
+
+ * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
+ * i386-tbl.h: Regenerated.
+
+2010-07-29 DJ Delorie <dj@redhat.com>
+
+ * rx-decode.opc (SRR): New.
+ (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
+ r0,r0) and NOP3 (max r0,r0) special cases.
+ * rx-decode.c: Regenerate.
+
+2010-07-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c: Add 0F to VEX opcode enums.
+
+2010-07-27 DJ Delorie <dj@redhat.com>
+
+ * rx-decode.opc (store_flags): Remove, replace with F_* macros.
+ (rx_decode_opcode): Likewise.
+ * rx-decode.c: Regenerate.
+
+2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
+ Ina Pandit <ina.pandit@kpitcummins.com>
+
+ * v850-dis.c (v850_sreg_names): Updated structure for system
+ registers.
+ (float_cc_names): new structure for condition codes.
+ (print_value): Update the function that prints value.
+ (get_operand_value): New function to get the operand value.
+ (disassemble): Updated to handle the disassembly of instructions.
+ (print_insn_v850): Updated function to print instruction for different
+ families.
+ * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
+ extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
+ extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
+ insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
+ extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
+ extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
+ extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
+ insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
+ (insert_d8_7, insert_d5_4, insert_i5div): Remove.
+ (v850_operands): Update with the relocation name. Also update
+ the instructions with specific set of processors.
+
+2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
+
+ * arm-dis.c (print_insn_arm): Add cases for printing more
+ symbolic operands.
+ (print_insn_thumb32): Likewise.
+
+2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-dis.c (print_insn_mips): Correct branch instruction type
+ determination.
+
+2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
+ type and delay slot determination.
+ (print_insn_mips16): Extend branch instruction type and delay
+ slot determination to cover all instructions.
+ * mips16-opc.c (BR): Remove macro.
+ (UBR, CBR): New macros.
+ (mips16_opcodes): Update branch annotation for "b", "beqz",
+ "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
+ and "jrc".
+
+2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ AVX Programming Reference (June, 2010)
+ * i386-dis.c (mod_table): Replace rdrnd with rdrand.
+ * i386-opc.tbl: Likewise.
+ * i386-tbl.h: Regenerated.
+
+2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
+
2010-07-03 Andreas Schwab <schwab@linux-m68k.org>
* ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
* i386-opc.h (CpuXsaveopt): New.
- (CpuFSGSBase):Likewise.
+ (CpuFSGSBase): Likewise.
(CpuRdRnd): Likewise.
(CpuF16C): Likewise.
(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and