/* This file is automatically generated by aarch64-gen. Do not edit! */
-/* Copyright (C) 2012-2021 Free Software Foundation, Inc.
+/* Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
case 33:
case 34:
case 35:
- case 221:
+ case 222:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
case 189:
case 190:
case 215:
- case 220:
+ case 221:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 219:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ case 220:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 223:
+ case 224:
+ case 225:
+ return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}
}