{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector element list"},
- {AARCH64_OPND_CLASS_CP_REG, "Cn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"},
- {AARCH64_OPND_CLASS_CP_REG, "Cm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a left shift amount for an AdvSIMD register"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a right shift amount for an AdvSIMD register"},
{AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"},
{AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate1}, "a 2-bit rotation specifier for complex arithmetic operations"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate2}, "a 2-bit rotation specifier for complex arithmetic operations"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate3}, "a 1-bit rotation specifier for complex arithmetic operations"},
{AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"},
{AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "one of the standard conditions, excluding AL and NV."},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"},
static const unsigned op_enum_table [] =
{
0,
- 860,
- 861,
- 862,
+ 863,
+ 864,
865,
- 866,
- 867,
868,
869,
- 863,
- 864,
870,
871,
- 893,
- 894,
- 895,
+ 872,
+ 866,
+ 867,
+ 873,
+ 874,
+ 896,
+ 897,
898,
- 899,
- 900,
901,
902,
- 896,
- 897,
903,
904,
- 952,
- 953,
- 954,
+ 905,
+ 899,
+ 900,
+ 906,
+ 907,
955,
+ 956,
+ 957,
+ 958,
12,
- 627,
- 628,
- 1147,
- 1149,
- 1151,
- 959,
+ 630,
+ 631,
1150,
- 1148,
- 311,
- 615,
- 626,
+ 1152,
+ 1154,
+ 962,
+ 1153,
+ 1151,
+ 312,
+ 618,
+ 629,
+ 628,
+ 960,
625,
- 957,
622,
- 619,
- 611,
- 610,
- 617,
- 618,
+ 614,
+ 613,
+ 620,
621,
- 623,
624,
- 967,
- 655,
+ 626,
+ 627,
+ 970,
658,
661,
- 656,
+ 664,
659,
- 804,
- 171,
+ 662,
+ 807,
172,
173,
174,
- 507,
- 744,
- 380,
- 382,
- 404,
- 406,
- 1212,
- 1217,
- 1210,
- 1209,
- 1213,
+ 175,
+ 510,
+ 747,
+ 383,
+ 385,
+ 407,
+ 409,
+ 1215,
1220,
- 1222,
+ 1213,
+ 1212,
+ 1216,
1223,
- 1219,
1225,
- 1224,
+ 1226,
+ 1222,
+ 1228,
+ 1227,
+ 129,
};
/* Given the opcode enumerator OP, return the pointer to the corresponding