FLD_immr,
FLD_immb,
FLD_immh,
+ FLD_S_imm10,
FLD_N,
FLD_index,
FLD_index2,
FLD_b5,
FLD_b40,
FLD_scale,
+ FLD_SVE_M_4,
+ FLD_SVE_M_14,
+ FLD_SVE_M_16,
+ FLD_SVE_N,
+ FLD_SVE_Pd,
+ FLD_SVE_Pg3,
+ FLD_SVE_Pg4_5,
+ FLD_SVE_Pg4_10,
+ FLD_SVE_Pg4_16,
+ FLD_SVE_Pm,
+ FLD_SVE_Pn,
+ FLD_SVE_Pt,
+ FLD_SVE_Rm,
+ FLD_SVE_Rn,
+ FLD_SVE_Vd,
+ FLD_SVE_Vm,
+ FLD_SVE_Vn,
+ FLD_SVE_Za_5,
+ FLD_SVE_Za_16,
+ FLD_SVE_Zd,
+ FLD_SVE_Zm_5,
+ FLD_SVE_Zm_16,
+ FLD_SVE_Zn,
+ FLD_SVE_Zt,
+ FLD_SVE_i1,
+ FLD_SVE_imm3,
+ FLD_SVE_imm4,
+ FLD_SVE_imm5,
+ FLD_SVE_imm5b,
+ FLD_SVE_imm6,
+ FLD_SVE_imm7,
+ FLD_SVE_imm8,
+ FLD_SVE_imm9,
+ FLD_SVE_immr,
+ FLD_SVE_imms,
+ FLD_SVE_msz,
+ FLD_SVE_pattern,
+ FLD_SVE_prfop,
+ FLD_SVE_sz,
+ FLD_SVE_tsz,
+ FLD_SVE_tszh,
+ FLD_SVE_tszl_8,
+ FLD_SVE_tszl_19,
+ FLD_SVE_xs_14,
+ FLD_SVE_xs_22,
+ FLD_rotate1,
+ FLD_rotate2,
+ FLD_rotate3,
};
/* Field description. */
value by 2 to get the value
of an immediate operand. */
#define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
+#define OPD_F_OD_MASK 0x00000060 /* Operand-dependent data. */
+#define OPD_F_OD_LSB 5
+#define OPD_F_NO_ZR 0x00000080 /* ZR index not allowed. */
static inline bfd_boolean
operand_has_inserter (const aarch64_operand *operand)
return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
}
+/* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
+static inline unsigned int
+get_operand_specific_data (const aarch64_operand *operand)
+{
+ return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
+}
+
/* Return the total width of the operand *OPERAND. */
static inline unsigned
get_operand_fields_width (const aarch64_operand *operand)
{
return extract_field_2 (&fields[kind], code, mask);
}
+
+extern aarch64_insn
+extract_fields (aarch64_insn code, aarch64_insn mask, ...);
\f
/* Inline functions selecting operand to do the encoding/decoding for a
certain instruction bit-field. */