/* ARC target-dependent stuff. Extension structure access functions
- Copyright (C) 1995-2016 Free Software Foundation, Inc.
+ Copyright (C) 1995-2017 Free Software Foundation, Inc.
This file is part of libopcodes.
struct ExtAuxRegister
{
- long address;
- char* name;
- struct ExtAuxRegister* next;
+ long address;
+ char * name;
+ struct ExtAuxRegister * next;
};
struct ExtCoreRegister
{
short number;
enum ExtReadWrite rw;
- char* name;
+ char * name;
};
struct arcExtMap
struct ExtAuxRegister* auxRegisters;
struct ExtInstruction* instructions[INST_HASH_SIZE];
struct ExtCoreRegister coreRegisters[NUM_EXT_CORE];
- char* condCodes[NUM_EXT_COND];
+ char * condCodes[NUM_EXT_COND];
};
arc_extension_map.
coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name
= xstrdup (name);
+ break;
}
case EXT_COND_CODE:
/* Get the name of an extension instruction. */
const extInstruction_t *
-arcExtMap_insn (int opcode, int insn)
+arcExtMap_insn (int opcode, unsigned long long insn)
{
/* Here the following tasks need to be done. First of all, the
opcode stored in the Extension Map is the real opcode. However,
arcExtMap_coreRegName (int regnum)
{
if (regnum < FIRST_EXTENSION_CORE_REGISTER
- || regnum > LAST_EXTENSION_CONDITION_CODE)
+ || regnum > LAST_EXTENSION_CORE_REGISTER)
return NULL;
return arc_extension_map.
coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name;
arcExtMap_coreReadWrite (int regnum)
{
if (regnum < FIRST_EXTENSION_CORE_REGISTER
- || regnum > LAST_EXTENSION_CONDITION_CODE)
+ || regnum > LAST_EXTENSION_CORE_REGISTER)
return REG_INVALID;
return arc_extension_map.
coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw;
insn != NULL; insn = insn->next)
{
printf ("INST: 0x%02x 0x%02x ", insn->major, insn->minor);
- if (insn->flags & ARC_SYNTAX_2OP)
- printf ("SYNTAX_2OP");
- else if (insn->flags & ARC_SYNTAX_3OP)
- printf ("SYNTAX_3OP");
- else
- printf ("SYNTAX_UNK");
+ switch (insn->flags & ARC_SYNTAX_MASK)
+ {
+ case ARC_SYNTAX_2OP:
+ printf ("SYNTAX_2OP");
+ break;
+ case ARC_SYNTAX_3OP:
+ printf ("SYNTAX_3OP");
+ break;
+ case ARC_SYNTAX_1OP:
+ printf ("SYNTAX_1OP");
+ break;
+ case ARC_SYNTAX_NOP:
+ printf ("SYNTAX_NOP");
+ break;
+ default:
+ printf ("SYNTAX_UNK");
+ break;
+ }
if (insn->flags & 0x10)
printf ("|MODIFIER");
struct ExtCoreRegister reg = arc_extension_map.coreRegisters[i];
if (reg.name)
- printf ("CORE: %s %d %s\n", reg.name, reg.number,
- ExtReadWrite_image (reg.rw));
+ printf ("CORE: 0x%04x %s %s\n", reg.number,
+ ExtReadWrite_image (reg.rw),
+ reg.name);
}
for (i = 0; i < NUM_EXT_COND; i++)
int count;
/* Check for the class to see how many instructions we generate. */
- switch (einsn->flags & (ARC_SYNTAX_3OP | ARC_SYNTAX_2OP))
+ switch (einsn->flags & ARC_SYNTAX_MASK)
{
case ARC_SYNTAX_3OP:
count = (einsn->modsyn & ARC_OP1_MUST_BE_IMM) ? 10 : 20;
case ARC_SYNTAX_2OP:
count = (einsn->flags & 0x10) ? 7 : 6;
break;
+ case ARC_SYNTAX_1OP:
+ count = 3;
+ break;
+ case ARC_SYNTAX_NOP:
+ count = 1;
+ break;
default:
count = 0;
break;
INSN3OP_C0LL (einsn->major, einsn->minor), MINSN3OP_C0LL,
arc_target, arg_32bit_zalimmlimm, lflags_ccf);
}
+ else if (einsn->flags & ARC_SYNTAX_1OP)
+ {
+ if (einsn->suffix & ARC_SUFFIX_COND)
+ *errmsg = "Suffix SUFFIX_COND ignored";
+
+ INSERT_XOP (q, einsn->name,
+ INSN2OP (einsn->major, 0x3F) | FIELDB (einsn->minor),
+ MINSN2OP_0C, arc_target, arg_32bit_rc, lflags_f);
+
+ INSERT_XOP (q, einsn->name,
+ INSN2OP (einsn->major, 0x3F) | FIELDB (einsn->minor)
+ | (0x01 << 22), MINSN2OP_0U, arc_target, arg_32bit_u6,
+ lflags_f);
+
+ INSERT_XOP (q, einsn->name,
+ INSN2OP (einsn->major, 0x3F) | FIELDB (einsn->minor)
+ | FIELDC (62), MINSN2OP_0L, arc_target, arg_32bit_limm,
+ lflags_f);
+
+ }
+ else if (einsn->flags & ARC_SYNTAX_NOP)
+ {
+ if (einsn->suffix & ARC_SUFFIX_COND)
+ *errmsg = "Suffix SUFFIX_COND ignored";
+
+ INSERT_XOP (q, einsn->name,
+ INSN2OP (einsn->major, 0x3F) | FIELDB (einsn->minor)
+ | (0x01 << 22), MINSN2OP_0L, arc_target, arg_none, lflags_f);
+ }
else
{
*errmsg = "Unknown syntax";