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sim: allow the environment configure option everywhere
[binutils-gdb.git] / opcodes / arm-dis.c
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index cff4b3fcb6d260b664e348541098958260c10e77..2695101b4bd44515c9c691097edb56b531156a1c 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1,5 +1,5 @@
 /* Instruction printing code for the ARM
-   Copyright (C) 1994-2015 Free Software Foundation, Inc.
+   Copyright (C) 1994-2016 Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
    Modification by James G. Smith (jsmith@cygnus.co.uk)
 
@@ -1581,34 +1581,34 @@ static const struct opcode32 arm_opcodes[] =
     0x0320f005, 0x0fffffff, "sevl"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
-    0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
+    0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
   /* CRC32 instructions.  */
   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
@@ -1666,9 +1666,9 @@ static const struct opcode32 arm_opcodes[] =
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
 
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
@@ -2335,8 +2335,10 @@ static const struct opcode16 thumb_opcodes[] =
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
 
   /* ARM V6T2 instructions.  */
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
+    0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
+    0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
 
   /* ARM V6.  */
@@ -2524,6 +2526,12 @@ static const struct opcode16 thumb_opcodes[] =
    makes heavy use of special-case bit patterns.  */
 static const struct opcode32 thumb32_opcodes[] =
 {
+  /* V8-M instructions.  */
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
+    0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
+    0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
+
   /* V8 instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     0xf3af8005, 0xffffffff, "sevl%c.w"},
@@ -2605,7 +2613,7 @@ static const struct opcode32 thumb32_opcodes[] =
     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
 
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     0xf3bf8f2f, 0xffffffff, "clrex%c"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
@@ -2633,9 +2641,9 @@ static const struct opcode32 thumb32_opcodes[] =
     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
@@ -2653,7 +2661,7 @@ static const struct opcode32 thumb32_opcodes[] =
     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
@@ -2761,7 +2769,7 @@ static const struct opcode32 thumb32_opcodes[] =
     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
@@ -2829,7 +2837,7 @@ static const struct opcode32 thumb32_opcodes[] =
     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
@@ -2877,11 +2885,11 @@ static const struct opcode32 thumb32_opcodes[] =
     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
@@ -2903,7 +2911,7 @@ static const struct opcode32 thumb32_opcodes[] =
     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},