%<bitfield>G print as an iWMMXt general purpose or control register
%<bitfield>D print as a NEON D register
%<bitfield>Q print as a NEON Q register
+ %<bitfield>E print a quarter-float immediate value
%y<code> print a single precision VFP reg.
Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
- 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
+ 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
- 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
+ 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000a10, 0xfe800f10,
"vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf3000b10, 0xff800f10,
+ "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf3000c10, 0xff800f10,
+ "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
/* One register and an immediate value. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800a40, 0xfe800f50,
"vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf2800e40, 0xff800f50,
+ "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf2800f40, 0xff800f50,
+ "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf3800e40, 0xff800f50,
+ "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf3800f40, 0xff800f50,
+ "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
+ },
/* Element and structure load/store. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
+ /* Privileged Access Never extension instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
+ 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
+
/* Virtualization Extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
/* ARM V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
/* ARM V6K no-argument instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
%X print "\t; unpredictable <IT:code>" if conditional
%<bitfield>d print bitfield in decimal
+ %<bitfield>D print bitfield plus one in decimal
%<bitfield>W print bitfield*4 in decimal
%<bitfield>r print bitfield as an ARM register
%<bitfield>R as %<>r but r15 is UNPREDICTABLE
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
+ 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
+ 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
/* Is ``imm'' a negative number? */
if (imm & 0x40)
- imm |= (-1 << 7);
+ imm -= 0x80;
func (stream, "%d", imm);
}
func (stream, "%ld", value);
value_in_comment = value;
break;
+ case 'E':
+ {
+ /* Converts immediate 8 bit back to float value. */
+ unsigned floatVal = (value & 0x80) << 24
+ | (value & 0x3F) << 19
+ | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
+
+ /* Quarter float have a maximum value of 31.0.
+ Get floating point value multiplied by 1e7.
+ The maximum value stays in limit of a 32-bit int. */
+ unsigned decVal =
+ (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
+ (16 + (value & 0xF));
+
+ if (!(decVal % 1000000))
+ func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
+ floatVal, value & 0x80 ? '-' : ' ',
+ decVal / 10000000,
+ decVal % 10000000 / 1000000);
+ else if (!(decVal % 10000))
+ func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
+ floatVal, value & 0x80 ? '-' : ' ',
+ decVal / 10000000,
+ decVal % 10000000 / 10000);
+ else
+ func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
+ floatVal, value & 0x80 ? '-' : ' ',
+ decVal / 10000000, decVal % 10000000);
+ break;
+ }
case 'k':
{
int from = (given & (1 << 7)) ? 32 : 16;
value_in_comment = val;
break;
+ case 'D':
+ func (stream, "%lu", val + 1);
+ value_in_comment = val + 1;
+ break;
+
case 'W':
func (stream, "%lu", val * 4);
value_in_comment = val * 4;
select_arm_features (unsigned long mach,
arm_feature_set * features)
{
-#undef ARM_FEATURE_LOW
-#define ARM_FEATURE_LOW(ARCH1,CEXT) \
- features->core[0] = (ARCH1); \
- features->core[1] = 0; \
- features->coproc = (CEXT) | FPU_FPA; \
- return
-
-#undef ARM_FEATURE_CORE_LOW
-#define ARM_FEATURE_CORE_LOW(ARCH1) \
- features->core[0] = (ARCH1); \
- features->core[1] = 0; \
- features->coproc = FPU_FPA; \
- return
+#undef ARM_SET_FEATURES
+#define ARM_SET_FEATURES(FSET) \
+ { \
+ const arm_feature_set fset = FSET; \
+ arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
+ ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
+ }
switch (mach)
{
- case bfd_mach_arm_2: ARM_ARCH_V2;
- case bfd_mach_arm_2a: ARM_ARCH_V2S;
- case bfd_mach_arm_3: ARM_ARCH_V3;
- case bfd_mach_arm_3M: ARM_ARCH_V3M;
- case bfd_mach_arm_4: ARM_ARCH_V4;
- case bfd_mach_arm_4T: ARM_ARCH_V4T;
- case bfd_mach_arm_5: ARM_ARCH_V5;
- case bfd_mach_arm_5T: ARM_ARCH_V5T;
- case bfd_mach_arm_5TE: ARM_ARCH_V5TE;
- case bfd_mach_arm_XScale: ARM_ARCH_XSCALE;
- case bfd_mach_arm_ep9312: ARM_FEATURE_LOW (ARM_AEXT_V4T, \
- ARM_CEXT_MAVERICK \
- | FPU_MAVERICK);
- case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT;
- case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
+ case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
+ case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
+ case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
+ case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
+ case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
+ case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
+ case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
+ case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
+ case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
+ case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
+ case bfd_mach_arm_ep9312:
+ ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
+ ARM_CEXT_MAVERICK | FPU_MAVERICK));
+ break;
+ case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
+ case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
/* If the machine type is unknown allow all
architecture types and all extensions. */
- case bfd_mach_arm_unknown: ARM_FEATURE_LOW (-1UL, -1UL);
+ case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
default:
abort ();
}
+
+#undef ARM_SET_FEATURES
}
projects / binutils-gdb.git / blobdiff