/* Instruction printing code for the ARM
- Copyright (C) 1994-2019 Free Software Foundation, Inc.
+ Copyright (C) 1994-2023 Free Software Foundation, Inc.
Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
Modification by James G. Smith (jsmith@cygnus.co.uk)
#include "elf/arm.h"
#include "mach-o.h"
-/* FIXME: Belongs in global header. */
-#ifndef strneq
-#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
-#endif
-
/* Cached mapping symbol state. */
enum map_type
{
MVE_VSUB_FP_T2,
MVE_VSUB_VEC_T1,
MVE_VSUB_VEC_T2,
+ MVE_VAND,
+ MVE_VBRSR,
+ MVE_VCLS,
+ MVE_VCLZ,
+ MVE_VCTP,
+ MVE_VMAX,
+ MVE_VMAXA,
+ MVE_VMAXNM_FP,
+ MVE_VMAXNMA_FP,
+ MVE_VMAXNMV_FP,
+ MVE_VMAXNMAV_FP,
+ MVE_VMAXV,
+ MVE_VMAXAV,
+ MVE_VMIN,
+ MVE_VMINA,
+ MVE_VMINNM_FP,
+ MVE_VMINNMA_FP,
+ MVE_VMINNMV_FP,
+ MVE_VMINNMAV_FP,
+ MVE_VMINV,
+ MVE_VMINAV,
+ MVE_VMLA,
+ MVE_VMUL_FP_T1,
+ MVE_VMUL_FP_T2,
+ MVE_VMUL_VEC_T1,
+ MVE_VMUL_VEC_T2,
+ MVE_VMULH,
+ MVE_VRMULH,
+ MVE_VNEG_FP,
+ MVE_VNEG_VEC,
+ MVE_VPNOT,
+ MVE_VPSEL,
+ MVE_VQABS,
+ MVE_VQADD_T1,
+ MVE_VQADD_T2,
+ MVE_VQSUB_T1,
+ MVE_VQSUB_T2,
+ MVE_VQNEG,
+ MVE_VREV16,
+ MVE_VREV32,
+ MVE_VREV64,
+ MVE_LSLL,
+ MVE_LSLLI,
+ MVE_LSRL,
+ MVE_ASRL,
+ MVE_ASRLI,
+ MVE_SQRSHRL,
+ MVE_SQRSHR,
+ MVE_UQRSHL,
+ MVE_UQRSHLL,
+ MVE_UQSHL,
+ MVE_UQSHLL,
+ MVE_URSHRL,
+ MVE_URSHR,
+ MVE_SRSHRL,
+ MVE_SRSHR,
+ MVE_SQSHLL,
+ MVE_SQSHL,
+ MVE_CINC,
+ MVE_CINV,
+ MVE_CNEG,
+ MVE_CSINC,
+ MVE_CSINV,
+ MVE_CSET,
+ MVE_CSETM,
+ MVE_CSNEG,
+ MVE_CSEL,
MVE_NONE
};
UNDEF_SIZE_2, /* undefined because size == 2. */
UNDEF_SIZE_3, /* undefined because size == 3. */
UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
+ UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
const char * assembler; /* How to disassemble this insn. */
};
+struct cdeopcode32
+{
+ arm_feature_set arch; /* Architecture defining this insn. */
+ uint8_t coproc_shift; /* coproc is this far into op. */
+ uint16_t coproc_mask; /* Length of coproc field in op. */
+ unsigned long value; /* If arch is 0 then value is a sentinel. */
+ unsigned long mask; /* Recognise insn if (op & mask) == value. */
+ const char * assembler; /* How to disassemble this insn. */
+};
+
/* MVE opcodes. */
struct mopcode32
%% %
%c print condition code (always bits 28-31 in ARM mode)
+ %b print condition code allowing cp_num == 9
%q print shifter argument
%u print condition code (unconditional in ARM mode,
UNPREDICTABLE if not AL in Thumb)
SENTINEL_GENERIC_START
} opcode_sentinels;
-#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
-#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
-#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
-#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
+#define UNDEFINED_INSTRUCTION "\t\t@ <UNDEFINED> instruction: %0-31x"
+#define UNKNOWN_INSTRUCTION_32BIT "\t\t@ <UNDEFINED> instruction: %08x"
+#define UNKNOWN_INSTRUCTION_16BIT "\t\t@ <UNDEFINED> instruction: %04x"
+#define UNPREDICTABLE_INSTRUCTION "\t@ <UNPREDICTABLE>"
/* Common coprocessor opcodes shared between Arm and Thumb-2. */
+/* print_insn_cde recognizes the following format control codes:
+
+ %% %
+
+ %a print 'a' iff bit 28 is 1
+ %p print bits 8-10 as coprocessor
+ %<bitfield>d print as decimal
+ %<bitfield>r print as an ARM register
+ %<bitfield>n print as an ARM register but r15 is APSR_nzcv
+ %<bitfield>T print as an ARM register + 1
+ %<bitfield>R as %r but r13 is UNPREDICTABLE
+ %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
+ %j print immediate taken from bits (16..21,7,0..5)
+ %k print immediate taken from bits (20..21,7,0..5).
+ %l print immediate taken from bits (20..22,7,4..5). */
+
+/* At the moment there is only one valid position for the coprocessor number,
+ and hence that's encoded in the macro below. */
+#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
+ { ARCH, 8, 7, VALUE, MASK, ASM }
+static const struct cdeopcode32 cde_opcodes[] =
+{
+ /* Custom Datapath Extension instructions. */
+ CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+ 0xee000000, 0xefc00840,
+ "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"),
+ CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+ 0xee000040, 0xefc00840,
+ "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"),
+
+ CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+ 0xee400000, 0xefc00840,
+ "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"),
+ CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+ 0xee400040, 0xefc00840,
+ "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"),
+
+ CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+ 0xee800000, 0xef800840,
+ "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
+ CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+ 0xee800040, 0xef800840,
+ "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
+
+ CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+ 0xec200000, 0xeeb00840,
+ "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"),
+ CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+ 0xec200040, 0xeeb00840,
+ "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"),
+
+ CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+ 0xec300000, 0xeeb00840,
+ "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"),
+ CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+ 0xec300040, 0xeeb00840,
+ "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"),
+
+ CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+ 0xec800000, 0xee800840,
+ "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"),
+ CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+ 0xec800040, 0xee800840,
+ "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"),
+
+ CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
+
+};
+
static const struct sopcode32 coprocessor_opcodes[] =
{
/* XScale instructions. */
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0ff0,
- "mia%c\tacc0, %0-3r, %12-15r"},
+ "mia%c\t%{R:acc0%}, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0ff0,
- "miaph%c\tacc0, %0-3r, %12-15r"},
+ "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
+ 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
+ 0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
+ 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"},
/* Intel Wireless MMX technology instructions. */
{ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
+ 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
+ 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
+ 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
+ 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
+ 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
+ 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
+ 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
+ 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
+ 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
+ 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
+ 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
+ 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
+ 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
+ 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
/* Data transfer between ARM and NEON registers. */
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
+ 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
+ 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
+ 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
+ 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
+ 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
+ 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"},
/* Half-precision conversion instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
/* Floating point coprocessor (VFP) instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
- {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
+ 0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"},
+ {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
+ 0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
+ 0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
+ 0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
+ 0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
+ 0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
+ 0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
+ 0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ 0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ 0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
+ 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
- {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
+ 0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"},
+ {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
+ 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
+ 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
+ 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
+ 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
+ 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
+ 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
+ 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
- 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
+ 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
- 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
+ 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
+ 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
- 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
+ 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
- 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
+ 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
- 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
+ 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
- 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
+ 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
- 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
+ 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
- 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
+ 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
- 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
+ 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
/* Cirrus coprocessor instructions. */
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
+ 0x0d100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
+ 0x0c100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
+ 0x0d500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
+ 0x0c500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
+ 0x0d100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
+ 0x0c100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
+ 0x0d500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
+ 0x0c500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
+ 0x0d000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
+ 0x0c000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
+ 0x0d400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
+ 0x0c400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
+ 0x0d000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
+ 0x0c000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
+ 0x0d400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
+ 0x0c400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
+ 0x0e000450, 0x0ff00ff0, "cfmvsr%c\t%{R:mvf%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
+ 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
+ 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\t%{R:mvd%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
+ 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
+ 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\t%{R:mvd%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
+ 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
+ 0x0e000510, 0x0ff00fff, "cfmv64lr%c\t%{R:mvdx%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
+ 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
+ 0x0e000530, 0x0ff00fff, "cfmv64hr%c\t%{R:mvdx%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
+ 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
+ 0x0e200440, 0x0ff00fff, "cfmval32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
+ 0x0e100440, 0x0ff00fff, "cfmv32al%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
+ 0x0e200460, 0x0ff00fff, "cfmvam32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
+ 0x0e100460, 0x0ff00fff, "cfmv32am%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
+ 0x0e200480, 0x0ff00fff, "cfmvah32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
+ 0x0e100480, 0x0ff00fff, "cfmv32ah%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
+ 0x0e2004a0, 0x0ff00fff, "cfmva32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
+ 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
+ 0x0e2004c0, 0x0ff00fff, "cfmva64%c\t%{R:mvax%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
+ 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\t%{R:mvdx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
+ 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\t%{R:dspsc%}, %{R:mvdx%12-15d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
+ 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\t%{R:mvdx%12-15d%}, %{R:dspsc%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
+ 0x0e000400, 0x0ff00fff, "cfcpys%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
+ 0x0e000420, 0x0ff00fff, "cfcpyd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
+ 0x0e000460, 0x0ff00fff, "cfcvtsd%c\t%{R:mvd%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
+ 0x0e000440, 0x0ff00fff, "cfcvtds%c\t%{R:mvf%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
+ 0x0e000480, 0x0ff00fff, "cfcvt32s%c\t%{R:mvf%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
+ 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\t%{R:mvd%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
+ 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\t%{R:mvf%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
+ 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\t%{R:mvd%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
+ 0x0e100580, 0x0ff00fff, "cfcvts32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
+ 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
+ 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
+ 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
+ 0x0e000550, 0x0ff00ff0, "cfrshl32%c\t%{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
+ 0x0e000570, 0x0ff00ff0, "cfrshl64%c\t%{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
+ 0x0e000500, 0x0ff00f10, "cfsh32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{I:#%I%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
+ 0x0e200500, 0x0ff00f10, "cfsh64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{I:#%I%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
+ 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
+ 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
+ 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
+ 0x0e300400, 0x0ff00fff, "cfabss%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
+ 0x0e300420, 0x0ff00fff, "cfabsd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
+ 0x0e300440, 0x0ff00fff, "cfnegs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
+ 0x0e300460, 0x0ff00fff, "cfnegd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
+ 0x0e300480, 0x0ff00ff0, "cfadds%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
+ 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
+ 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
+ 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
+ 0x0e100400, 0x0ff00ff0, "cfmuls%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
+ 0x0e100420, 0x0ff00ff0, "cfmuld%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
+ 0x0e300500, 0x0ff00fff, "cfabs32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
+ 0x0e300520, 0x0ff00fff, "cfabs64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
+ 0x0e300540, 0x0ff00fff, "cfneg32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
+ 0x0e300560, 0x0ff00fff, "cfneg64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e300580, 0x0ff00ff0, "cfadd32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
+ 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
+ 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e100500, 0x0ff00ff0, "cfmul32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
+ 0x0e100520, 0x0ff00ff0, "cfmul64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e100540, 0x0ff00ff0, "cfmac32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e100560, 0x0ff00ff0, "cfmsc32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000600, 0x0ff00f10,
- "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ "cfmadd32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100600, 0x0ff00f10,
- "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ "cfmsub32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200600, 0x0ff00f10,
- "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ "cfmadda32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300600, 0x0ff00f10,
- "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ "cfmsuba32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
/* VFP Fused multiply add instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
- /* Generic coprocessor instructions. */
{ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
- 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
- 0x0c500000, 0x0ff00000,
- "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
- 0x0e000000, 0x0f000010,
- "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
- 0x0e10f010, 0x0f10f010,
- "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
- 0x0e100010, 0x0f100010,
- "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
- 0x0e000010, 0x0f100010,
- "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
- 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
- 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
-
- /* V6 coprocessor instructions. */
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xfc500000, 0xfff00000,
- "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xfc400000, 0xfff00000,
- "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
-
/* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
+ 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
+ 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
+ 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
+ 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
+ 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
+ 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
+ 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
+ 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
+ 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
+ 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"},
+
+ /* BFloat16 instructions. */
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+ 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
/* Dot Product instructions in the space of coprocessor 13. */
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
- 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
+ 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"},
/* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
+ 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
+ 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
+ 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
+ 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
+ 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
+ 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
+ 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
-
- /* V5 coprocessor instructions. */
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
- 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
- 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
- 0xfe000000, 0xff000010,
- "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
- 0xfe000010, 0xff100010,
- "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
- 0xfe100010, 0xff100010,
- "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
+ 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
/* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
cp_num: bit <11:8> == 0b1001.
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
+ 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
+ 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
+ 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
+ 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
{ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
};
+/* Generic coprocessor instructions. These are only matched if a more specific
+ SIMD or co-processor instruction does not match first. */
+
+static const struct sopcode32 generic_coprocessor_opcodes[] =
+{
+ /* Generic coprocessor instructions. */
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
+ 0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"},
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
+ 0x0c500000, 0x0ff00000,
+ "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ 0x0e000000, 0x0f000010,
+ "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ 0x0e10f010, 0x0f10f010,
+ "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ 0x0e100010, 0x0f100010,
+ "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ 0x0e000010, 0x0f100010,
+ "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ 0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ 0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
+
+ /* V6 coprocessor instructions. */
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
+ 0xfc500000, 0xfff00000,
+ "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
+ 0xfc400000, 0xfff00000,
+ "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"},
+
+ /* V5 coprocessor instructions. */
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ 0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ 0xfe000000, 0xff000010,
+ "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ 0xfe000010, 0xff100010,
+ "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ 0xfe100010, 0xff100010,
+ "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
+
+ {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
+};
+
/* Neon opcode table: This does not encode the top byte -- that is
checked by the print_insn_neon routine, as it depends on whether we are
doing thumb32 or arm32 disassembly. */
/* Extract. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2b00840, 0xffb00850,
- "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
+ "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2b00000, 0xffb00810,
- "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
+ "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
/* Data transfer between ARM and NEON registers. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
+ 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
+ 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
+ 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
+ 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
+ 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
+ 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
/* Move data element to all lanes. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
+ 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
+ 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
+ 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"},
/* Table lookup. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ /* BFloat16 instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+ 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+ 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+ 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+ 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+ 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+ 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"},
+
+ /* Matrix Multiply instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+ 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+ 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+ 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+ 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+ 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+ 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
+
/* Two registers, miscellaneous. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20300, 0xffb30fd0,
- "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
+ "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
/* Two registers and a shift amount. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880950, 0xfeb80fd0,
- "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
+ 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
+ 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
+ 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
+ 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900950, 0xfeb00fd0,
- "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
+ 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
+ 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
+ 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
+ 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
+ 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
+ 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
+ 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00950, 0xfea00fd0,
- "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
+ 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
+ 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
+ 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
+ 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
+ 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
+ 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
+ 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
+ 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00e10, 0xfea00e90,
- "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2a00c10, 0xfea00e90,
- "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
+ "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
/* Three registers of different lengths. */
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
%d print addr mode of MVE vldr[bhw] and vstr[bhw]
%u print 'U' (unsigned) or 'S' for various mve instructions
%i print MVE predicate(s) for vpt and vpst
+ %j print a 5-bit immediate from hw2[14:12,7:6]
+ %k print 48 if the 7th position bit is set else print 64.
%m print rounding mode for vcvt and vrint
%n print vector comparison code for predicated instruction
%s print size for various vcvt instructions
%<bitfield>r print as an ARM register
%<bitfield>d print the bitfield in decimal
%<bitfield>A print accumulate or not
+ %<bitfield>c print bitfield as a condition code
+ %<bitfield>C print bitfield as an inverted condition code
%<bitfield>Q print as a MVE Q register
%<bitfield>F print as a MVE S register
%<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
UNPREDICTABLE
+
+ %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
%<bitfield>s print size for vector predicate & non VMOV instructions
%<bitfield>I print carry flag or not
%<bitfield>i print immediate for vstr/vldr reg +/- imm
{
/* MVE. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPST,
0xfe310f4d, 0xffbf1fff,
"vpst%i"
},
/* Floating point VPT T1. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VPT_FP_T1,
0xee310f00, 0xefb10f50,
"vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
/* Floating point VPT T2. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VPT_FP_T2,
0xee310f40, 0xefb10f50,
"vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
/* Vector VPT T1. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPT_VEC_T1,
0xfe010f00, 0xff811f51,
"vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VPT T2. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPT_VEC_T2,
0xfe010f01, 0xff811f51,
"vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VPT T3. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPT_VEC_T3,
0xfe011f00, 0xff811f50,
"vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VPT T4. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPT_VEC_T4,
0xfe010f40, 0xff811f70,
"vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
/* Vector VPT T5. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPT_VEC_T5,
0xfe010f60, 0xff811f70,
"vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
/* Vector VPT T6. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPT_VEC_T6,
0xfe011f40, 0xff811f50,
"vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
/* Vector VBIC immediate. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VBIC_IMM,
0xef800070, 0xefb81070,
"vbic%v.i%8-11s\t%13-15,22Q, %E"},
/* Vector VBIC register. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VBIC_REG,
0xef100150, 0xffb11f51,
"vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VABAV. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VABAV,
0xee800f01, 0xefc10f51,
"vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
/* Vector VABD floating point. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VABD_FP,
0xff200d40, 0xffa11f51,
"vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VABD. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VABD_VEC,
0xef000740, 0xef811f51,
"vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VABS floating point. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VABS_FP,
0xFFB10740, 0xFFB31FD1,
"vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
/* Vector VABS. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VABS_VEC,
0xffb10340, 0xffb31fd1,
"vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
/* Vector VADD floating point T1. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VADD_FP_T1,
0xef000d40, 0xffa11f51,
"vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VADD floating point T2. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VADD_FP_T2,
0xee300f40, 0xefb11f70,
"vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VADD T1. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VADD_VEC_T1,
0xef000840, 0xff811f51,
"vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VADD T2. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VADD_VEC_T2,
0xee010f40, 0xff811f70,
"vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VADDLV. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VADDLV,
0xee890f00, 0xef8f1fd1,
"vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
/* Vector VADDV. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VADDV,
0xeef10f00, 0xeff31fd1,
"vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
/* Vector VADC. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VADC,
0xee300f00, 0xffb10f51,
"vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+ /* Vector VAND. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VAND,
+ 0xef000150, 0xffb11f51,
+ "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VBRSR register. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VBRSR,
+ 0xfe011e60, 0xff811f70,
+ "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+
/* Vector VCADD floating point. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCADD_FP,
0xfc800840, 0xfea11f51,
- "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
+ "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"},
/* Vector VCADD. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCADD_VEC,
0xfe000f00, 0xff810f51,
- "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
+ "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
+
+ /* Vector VCLS. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VCLS,
+ 0xffb00440, 0xffb31fd1,
+ "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
+
+ /* Vector VCLZ. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VCLZ,
+ 0xffb004c0, 0xffb31fd1,
+ "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
/* Vector VCMLA. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCMLA_FP,
0xfc200840, 0xfe211f51,
- "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
+ "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"},
/* Vector VCMP floating point T1. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCMP_FP_T1,
0xee310f00, 0xeff1ef50,
"vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VCMP floating point T2. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCMP_FP_T2,
0xee310f40, 0xeff1ef50,
"vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
/* Vector VCMP T1. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCMP_VEC_T1,
0xfe010f00, 0xffc1ff51,
"vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VCMP T2. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCMP_VEC_T2,
0xfe010f01, 0xffc1ff51,
"vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VCMP T3. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCMP_VEC_T3,
0xfe011f00, 0xffc1ff50,
"vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VCMP T4. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCMP_VEC_T4,
0xfe010f40, 0xffc1ff70,
"vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
/* Vector VCMP T5. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCMP_VEC_T5,
0xfe010f60, 0xffc1ff70,
"vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
/* Vector VCMP T6. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCMP_VEC_T6,
0xfe011f40, 0xffc1ff50,
"vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
/* Vector VDUP. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VDUP,
0xeea00b10, 0xffb10f5f,
"vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
/* Vector VEOR. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VEOR,
0xff000150, 0xffd11f51,
"veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VFMA, vector * scalar. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VFMA_FP_SCALAR,
0xee310e40, 0xefb11f70,
"vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VFMA floating point. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VFMA_FP,
0xef000c50, 0xffa11f51,
"vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VFMS floating point. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VFMS_FP,
0xef200c50, 0xffa11f51,
"vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VFMAS, vector * scalar. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VFMAS_FP_SCALAR,
0xee311e40, 0xefb11f70,
"vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VHADD T1. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VHADD_T1,
0xef000040, 0xef811f51,
"vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VHADD T2. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VHADD_T2,
0xee000f40, 0xef811f70,
"vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VHSUB T1. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VHSUB_T1,
0xef000240, 0xef811f51,
"vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VHSUB T2. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VHSUB_T2,
0xee001f40, 0xef811f70,
"vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VCMUL. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCMUL_FP,
0xee300e00, 0xefb10f50,
- "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
+ "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"},
+
+ /* Vector VCTP. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VCTP,
+ 0xf000e801, 0xffc0ffff,
+ "vctp%v.%20-21s\t%16-19r"},
/* Vector VDUP. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VDUP,
0xeea00b10, 0xffb10f5f,
"vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
/* Vector VRHADD. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRHADD,
0xef000140, 0xef811f51,
"vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VCVT. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCVT_FP_FIX_VEC,
0xef800c50, 0xef801cd1,
- "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
+ "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"},
/* Vector VCVT. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCVT_BETWEEN_FP_INT,
0xffb30640, 0xffb31e51,
"vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
/* Vector VCVT between single and half-precision float, bottom half. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCVT_FP_HALF_FP,
0xee3f0e01, 0xefbf1fd1,
"vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
/* Vector VCVT between single and half-precision float, top half. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCVT_FP_HALF_FP,
0xee3f1e01, 0xefbf1fd1,
"vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
/* Vector VCVT. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCVT_FROM_FP_TO_INT,
0xffb30040, 0xffb31c51,
"vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
/* Vector VDDUP. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VDDUP,
0xee011f6e, 0xff811f7e,
- "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
+ "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
/* Vector VDWDUP. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VDWDUP,
0xee011f60, 0xff811f70,
- "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
+ "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
/* Vector VHCADD. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VHCADD,
0xee000f00, 0xff810f51,
- "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
+ "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
/* Vector VIWDUP. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VIWDUP,
0xee010f60, 0xff811f70,
- "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
+ "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
/* Vector VIDUP. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VIDUP,
0xee010f6e, 0xff811f7e,
- "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
+ "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
/* Vector VLD2. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLD2,
0xfc901e00, 0xff901e5f,
"vld2%5d.%7-8s\t%B, [%16-19r]%w"},
/* Vector VLD4. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLD4,
0xfc901e01, 0xff901e1f,
"vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
/* Vector VLDRB gather load. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRB_GATHER_T1,
0xec900e00, 0xefb01e50,
"vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
/* Vector VLDRH gather load. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRH_GATHER_T2,
0xec900e10, 0xefb01e50,
"vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
/* Vector VLDRW gather load. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRW_GATHER_T3,
0xfc900f40, 0xffb01fd0,
"vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
/* Vector VLDRD gather load. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRD_GATHER_T4,
0xec900fd0, 0xefb01fd0,
"vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
/* Vector VLDRW gather load. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRW_GATHER_T5,
0xfd101e00, 0xff111f00,
- "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
+ "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
/* Vector VLDRD gather load, variant T6. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRD_GATHER_T6,
0xfd101f00, 0xff111f00,
- "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
+ "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
/* Vector VLDRB. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRB_T1,
0xec100e00, 0xee581e00,
"vldrb%v.%u%7-8s\t%13-15Q, %d"},
/* Vector VLDRH. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRH_T2,
0xec180e00, 0xee581e00,
"vldrh%v.%u%7-8s\t%13-15Q, %d"},
/* Vector VLDRB unsigned, variant T5. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRB_T5,
0xec101e00, 0xfe101f80,
"vldrb%v.u8\t%13-15,22Q, %d"},
/* Vector VLDRH unsigned, variant T6. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRH_T6,
0xec101e80, 0xfe101f80,
"vldrh%v.u16\t%13-15,22Q, %d"},
/* Vector VLDRW unsigned, variant T7. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRW_T7,
0xec101f00, 0xfe101f80,
"vldrw%v.u32\t%13-15,22Q, %d"},
+ /* Vector VMAX. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMAX,
+ 0xef000640, 0xef811f51,
+ "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VMAXA. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMAXA,
+ 0xee330e81, 0xffb31fd1,
+ "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
+
+ /* Vector VMAXNM floating point. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
+ MVE_VMAXNM_FP,
+ 0xff000f50, 0xffa11f51,
+ "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VMAXNMA floating point. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
+ MVE_VMAXNMA_FP,
+ 0xee3f0e81, 0xefbf1fd1,
+ "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
+
+ /* Vector VMAXNMV floating point. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
+ MVE_VMAXNMV_FP,
+ 0xeeee0f00, 0xefff0fd1,
+ "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
+
+ /* Vector VMAXNMAV floating point. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
+ MVE_VMAXNMAV_FP,
+ 0xeeec0f00, 0xefff0fd1,
+ "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
+
+ /* Vector VMAXV. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMAXV,
+ 0xeee20f00, 0xeff30fd1,
+ "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
+
+ /* Vector VMAXAV. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMAXAV,
+ 0xeee00f00, 0xfff30fd1,
+ "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
+
+ /* Vector VMIN. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMIN,
+ 0xef000650, 0xef811f51,
+ "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VMINA. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMINA,
+ 0xee331e81, 0xffb31fd1,
+ "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
+
+ /* Vector VMINNM floating point. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
+ MVE_VMINNM_FP,
+ 0xff200f50, 0xffa11f51,
+ "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VMINNMA floating point. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
+ MVE_VMINNMA_FP,
+ 0xee3f1e81, 0xefbf1fd1,
+ "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
+
+ /* Vector VMINNMV floating point. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
+ MVE_VMINNMV_FP,
+ 0xeeee0f80, 0xefff0fd1,
+ "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
+
+ /* Vector VMINNMAV floating point. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
+ MVE_VMINNMAV_FP,
+ 0xeeec0f80, 0xefff0fd1,
+ "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
+
+ /* Vector VMINV. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMINV,
+ 0xeee20f80, 0xeff30fd1,
+ "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
+
+ /* Vector VMINAV. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMINAV,
+ 0xeee00f80, 0xfff30fd1,
+ "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
+
+ /* Vector VMLA. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMLA,
+ 0xee010e40, 0xef811f70,
+ "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+
/* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
opcode aliasing. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMLALDAV,
0xee801e00, 0xef801f51,
"vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMLALDAV,
0xee800e00, 0xef801f51,
"vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
/* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMLADAV_T1,
0xeef00e00, 0xeff01f51,
"vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
/* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMLADAV_T2,
0xeef00f00, 0xeff11f51,
"vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
/* Vector VMLADAV T1 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMLADAV_T1,
0xeef01e00, 0xeff01f51,
"vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
/* Vector VMLADAV T2 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMLADAV_T2,
0xeef01f00, 0xeff11f51,
"vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
/* Vector VMLAS. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMLAS,
0xee011e40, 0xef811f70,
"vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
opcode aliasing. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRMLSLDAVH,
0xfe800e01, 0xff810f51,
"vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
/* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
opcdoe aliasing. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMLSLDAV,
0xee800e01, 0xff800f51,
"vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
/* Vector VMLSDAV T1 Variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMLSDAV_T1,
0xeef00e01, 0xfff00f51,
"vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
/* Vector VMLSDAV T2 Variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMLSDAV_T2,
0xfef00e01, 0xfff10f51,
"vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
/* Vector VMOV between gpr and half precision register, op == 0. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VMOV_HFP_TO_GP,
0xee000910, 0xfff00f7f,
"vmov.f16\t%7,16-19F, %12-15r"},
/* Vector VMOV between gpr and half precision register, op == 1. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VMOV_HFP_TO_GP,
0xee100910, 0xfff00f7f,
"vmov.f16\t%12-15r, %7,16-19F"},
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VMOV_GP_TO_VEC_LANE,
0xee000b10, 0xff900f1f,
- "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
+ "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"},
/* Vector VORR immediate to vector.
NOTE: MVE_VORR_IMM must appear in the table
before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VORR_IMM,
0xef800050, 0xefb810f0,
"vorr%v.i%8-11s\t%13-15,22Q, %E"},
/* Vector VQSHL T2 Variant.
NOTE: MVE_VQSHL_T2 must appear in the table before
before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHL_T2,
0xef800750, 0xef801fd1,
- "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQSHLU T3 Variant
NOTE: MVE_VQSHL_T2 must appear in the table before
before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHLU_T3,
0xff800650, 0xff801fd1,
- "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VRSHR
NOTE: MVE_VRSHR must appear in the table before
before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRSHR,
0xef800250, 0xef801fd1,
- "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSHL.
NOTE: MVE_VSHL must appear in the table before
before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHL_T1,
0xef800550, 0xff801fd1,
- "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSHR
NOTE: MVE_VSHR must appear in the table before
before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHR,
0xef800050, 0xef801fd1,
- "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSLI
NOTE: MVE_VSLI must appear in the table before
before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSLI,
0xff800550, 0xff801fd1,
- "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSRI
NOTE: MVE_VSRI must appear in the table before
before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSRI,
0xff800450, 0xff801fd1,
- "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
+
+ /* Vector VMOV immediate to vector,
+ undefinded for cmode == 1111 */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
/* Vector VMOV immediate to vector,
- cmode == 11x1 -> VMVN which is UNDEFINED
- for such a cmode. */
- {ARM_FEATURE_COPROC (FPU_MVE),
- MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
+ cmode == 1101 */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
+ "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
/* Vector VMOV immediate to vector. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV_IMM_TO_VEC,
0xef800050, 0xefb810d0,
"vmov%v.%5,8-11s\t%13-15,22Q, %E"},
/* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV2_VEC_LANE_TO_GP,
0xec000f00, 0xffb01ff0,
- "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
+ "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"},
/* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV2_VEC_LANE_TO_GP,
0xec000f10, 0xffb01ff0,
- "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
+ "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"},
/* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV2_GP_TO_VEC_LANE,
0xec100f00, 0xffb01ff0,
- "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
+ "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"},
/* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV2_GP_TO_VEC_LANE,
0xec100f10, 0xffb01ff0,
- "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
+ "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"},
/* Vector VMOV Vector lane to gpr. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VMOV_VEC_LANE_TO_GP,
0xee100b10, 0xff100f1f,
- "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
+ "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"},
/* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
to instruction opcode aliasing. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHLL_T1,
0xeea00f40, 0xefa00fd1,
- "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VMOVL long. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOVL,
0xeea00f40, 0xefa70fd1,
"vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
/* Vector VMOV and narrow. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOVN,
0xfe310e81, 0xffb30fd1,
"vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
/* Floating point move extract. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VMOVX,
0xfeb00a40, 0xffbf0fd0,
"vmovx.f16\t%22,12-15F, %5,0-3F"},
+ /* Vector VMUL floating-point T1 variant. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
+ MVE_VMUL_FP_T1,
+ 0xff000d50, 0xffa11f51,
+ "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VMUL floating-point T2 variant. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
+ MVE_VMUL_FP_T2,
+ 0xee310e60, 0xefb11f70,
+ "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+
+ /* Vector VMUL T1 variant. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMUL_VEC_T1,
+ 0xef000950, 0xff811f51,
+ "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VMUL T2 variant. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMUL_VEC_T2,
+ 0xee011e60, 0xff811f70,
+ "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+
+ /* Vector VMULH. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMULH,
+ 0xee010e01, 0xef811f51,
+ "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VRMULH. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VRMULH,
+ 0xee011e01, 0xef811f51,
+ "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
/* Vector VMULL integer. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMULL_INT,
0xee010e00, 0xef810f51,
"vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VMULL polynomial. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMULL_POLY,
0xee310e00, 0xefb10f51,
"vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VMVN immediate to vector. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMVN_IMM,
0xef800070, 0xefb810f0,
"vmvn%v.i%8-11s\t%13-15,22Q, %E"},
/* Vector VMVN register. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMVN_REG,
0xffb005c0, 0xffbf1fd1,
"vmvn%v\t%13-15,22Q, %1-3,5Q"},
+ /* Vector VNEG floating point. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
+ MVE_VNEG_FP,
+ 0xffb107c0, 0xffb31fd1,
+ "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
+
+ /* Vector VNEG. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VNEG_VEC,
+ 0xffb103c0, 0xffb31fd1,
+ "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
+
/* Vector VORN, vector bitwise or not. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VORN,
0xef300150, 0xffb11f51,
"vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VORR register. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VORR_REG,
0xef200150, 0xffb11f51,
"vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+ /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
+ "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
+ MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
+ array. */
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VMOV_VEC_TO_VEC,
+ 0xef200150, 0xffb11f51,
+ "vmov%v\t%13-15,22Q, %17-19,7Q"},
+
/* Vector VQDMULL T1 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQDMULL_T1,
0xee300f01, 0xefb10f51,
"vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+ /* Vector VPNOT. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VPNOT,
+ 0xfe310f4d, 0xffffffff,
+ "vpnot%v"},
+
+ /* Vector VPSEL. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VPSEL,
+ 0xfe310f01, 0xffb11f51,
+ "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VQABS. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VQABS,
+ 0xffb00740, 0xffb31fd1,
+ "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VQADD T1 variant. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VQADD_T1,
+ 0xef000050, 0xef811f51,
+ "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VQADD T2 variant. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VQADD_T2,
+ 0xee000f60, 0xef811f70,
+ "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+
/* Vector VQDMULL T2 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQDMULL_T2,
0xee300f60, 0xefb10f70,
"vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQMOVN. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQMOVN,
0xee330e01, 0xefb30fd1,
"vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
/* Vector VQMOVUN. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQMOVUN,
0xee310e81, 0xffb30fd1,
"vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
/* Vector VQDMLADH. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQDMLADH,
0xee000e00, 0xff810f51,
"vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VQRDMLADH. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRDMLADH,
0xee000e01, 0xff810f51,
"vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VQDMLAH. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQDMLAH,
- 0xee000e60, 0xef811f70,
+ 0xee000e60, 0xff811f70,
"vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQRDMLAH. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRDMLAH,
- 0xee000e40, 0xef811f70,
+ 0xee000e40, 0xff811f70,
"vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQDMLASH. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQDMLASH,
- 0xee001e60, 0xef811f70,
+ 0xee001e60, 0xff811f70,
"vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQRDMLASH. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRDMLASH,
- 0xee001e40, 0xef811f70,
+ 0xee001e40, 0xff811f70,
"vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQDMLSDH. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQDMLSDH,
0xfe000e00, 0xff810f51,
"vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VQRDMLSDH. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRDMLSDH,
0xfe000e01, 0xff810f51,
"vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VQDMULH T1 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQDMULH_T1,
0xef000b40, 0xff811f51,
"vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VQRDMULH T2 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRDMULH_T2,
0xff000b40, 0xff811f51,
"vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VQDMULH T3 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQDMULH_T3,
0xee010e60, 0xff811f70,
"vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQRDMULH T4 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRDMULH_T4,
0xfe010e60, 0xff811f70,
"vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+ /* Vector VQNEG. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VQNEG,
+ 0xffb007c0, 0xffb31fd1,
+ "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
+
/* Vector VQRSHL T1 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRSHL_T1,
0xef000550, 0xef811f51,
"vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
/* Vector VQRSHL T2 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRSHL_T2,
0xee331ee0, 0xefb31ff0,
"vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
/* Vector VQRSHRN. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRSHRN,
0xee800f41, 0xefa00fd1,
- "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQRSHRUN. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRSHRUN,
0xfe800fc0, 0xffa00fd1,
- "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQSHL T1 Variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHL_T1,
0xee311ee0, 0xefb31ff0,
"vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
/* Vector VQSHL T4 Variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHL_T4,
0xef000450, 0xef811f51,
"vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
/* Vector VQSHRN. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHRN,
0xee800f40, 0xefa00fd1,
- "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQSHRUN. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHRUN,
0xee800fc0, 0xffa00fd1,
- "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
+
+ /* Vector VQSUB T1 Variant. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VQSUB_T1,
+ 0xef000250, 0xef811f51,
+ "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VQSUB T2 Variant. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VQSUB_T2,
+ 0xee001f60, 0xef811f70,
+ "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+
+ /* Vector VREV16. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VREV16,
+ 0xffb00140, 0xffb31fd1,
+ "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
+
+ /* Vector VREV32. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VREV32,
+ 0xffb000c0, 0xffb31fd1,
+ "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
+
+ /* Vector VREV64. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_VREV64,
+ 0xffb00040, 0xffb31fd1,
+ "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
/* Vector VRINT floating point. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VRINT_FP,
0xffb20440, 0xffb31c51,
"vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
/* Vector VRMLALDAVH. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRMLALDAVH,
0xee800f00, 0xef811f51,
"vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
/* Vector VRMLALDAVH. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRMLALDAVH,
0xee801f00, 0xef811f51,
"vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
/* Vector VRSHL T1 Variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRSHL_T1,
0xef000540, 0xef811f51,
"vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
/* Vector VRSHL T2 Variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRSHL_T2,
0xee331e60, 0xefb31ff0,
"vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
/* Vector VRSHRN. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRSHRN,
0xfe800fc1, 0xffa00fd1,
- "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSBC. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSBC,
0xfe300f00, 0xffb10f51,
"vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VSHL T2 Variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHL_T2,
0xee311e60, 0xefb31ff0,
"vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
/* Vector VSHL T3 Variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHL_T3,
0xef000440, 0xef811f51,
"vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
/* Vector VSHLC. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHLC,
0xeea00fc0, 0xffa01ff0,
- "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
+ "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"},
/* Vector VSHLL T2 Variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHLL_T2,
0xee310e01, 0xefb30fd1,
- "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
+ "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"},
/* Vector VSHRN. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHRN,
0xee800fc1, 0xffa00fd1,
- "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VST2 no writeback. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VST2,
0xfc801e00, 0xffb01e5f,
"vst2%5d.%7-8s\t%B, [%16-19r]"},
/* Vector VST2 writeback. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VST2,
0xfca01e00, 0xffb01e5f,
"vst2%5d.%7-8s\t%B, [%16-19r]!"},
/* Vector VST4 no writeback. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VST4,
0xfc801e01, 0xffb01e1f,
"vst4%5-6d.%7-8s\t%B, [%16-19r]"},
/* Vector VST4 writeback. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VST4,
0xfca01e01, 0xffb01e1f,
"vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
/* Vector VSTRB scatter store, T1 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRB_SCATTER_T1,
0xec800e00, 0xffb01e50,
"vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
/* Vector VSTRH scatter store, T2 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRH_SCATTER_T2,
0xec800e10, 0xffb01e50,
"vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
/* Vector VSTRW scatter store, T3 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRW_SCATTER_T3,
0xec800e40, 0xffb01e50,
"vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
/* Vector VSTRD scatter store, T4 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRD_SCATTER_T4,
0xec800fd0, 0xffb01fd0,
"vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
/* Vector VSTRW scatter store, T5 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRW_SCATTER_T5,
0xfd001e00, 0xff111f00,
- "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
+ "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
/* Vector VSTRD scatter store, T6 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRD_SCATTER_T6,
0xfd001f00, 0xff111f00,
- "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
+ "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
/* Vector VSTRB. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRB_T1,
0xec000e00, 0xfe581e00,
"vstrb%v.%7-8s\t%13-15Q, %d"},
/* Vector VSTRH. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRH_T2,
0xec080e00, 0xfe581e00,
"vstrh%v.%7-8s\t%13-15Q, %d"},
/* Vector VSTRB variant T5. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRB_T5,
0xec001e00, 0xfe101f80,
"vstrb%v.8\t%13-15,22Q, %d"},
/* Vector VSTRH variant T6. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRH_T6,
0xec001e80, 0xfe101f80,
"vstrh%v.16\t%13-15,22Q, %d"},
/* Vector VSTRW variant T7. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRW_T7,
0xec001f00, 0xfe101f80,
"vstrw%v.32\t%13-15,22Q, %d"},
/* Vector VSUB floating point T1 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VSUB_FP_T1,
0xef200d40, 0xffa11f51,
"vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VSUB floating point T2 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VSUB_FP_T2,
0xee301f40, 0xefb11f70,
"vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VSUB T1 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSUB_VEC_T1,
0xff000840, 0xff811f51,
"vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VSUB T2 variant. */
- {ARM_FEATURE_COPROC (FPU_MVE),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSUB_VEC_T2,
0xee011f40, 0xff811f70,
"vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_ASRLI,
+ 0xea50012f, 0xfff1813f,
+ "asrl%c\t%17-19l, %9-11h, %j"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_ASRL,
+ 0xea50012d, 0xfff101ff,
+ "asrl%c\t%17-19l, %9-11h, %12-15S"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_LSLLI,
+ 0xea50010f, 0xfff1813f,
+ "lsll%c\t%17-19l, %9-11h, %j"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_LSLL,
+ 0xea50010d, 0xfff101ff,
+ "lsll%c\t%17-19l, %9-11h, %12-15S"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_LSRL,
+ 0xea50011f, 0xfff1813f,
+ "lsrl%c\t%17-19l, %9-11h, %j"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_SQRSHRL,
+ 0xea51012d, 0xfff1017f,
+ "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_SQRSHR,
+ 0xea500f2d, 0xfff00fff,
+ "sqrshr%c\t%16-19S, %12-15S"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_SQSHLL,
+ 0xea51013f, 0xfff1813f,
+ "sqshll%c\t%17-19l, %9-11h, %j"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_SQSHL,
+ 0xea500f3f, 0xfff08f3f,
+ "sqshl%c\t%16-19S, %j"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_SRSHRL,
+ 0xea51012f, 0xfff1813f,
+ "srshrl%c\t%17-19l, %9-11h, %j"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_SRSHR,
+ 0xea500f2f, 0xfff08f3f,
+ "srshr%c\t%16-19S, %j"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_UQRSHLL,
+ 0xea51010d, 0xfff1017f,
+ "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_UQRSHL,
+ 0xea500f0d, 0xfff00fff,
+ "uqrshl%c\t%16-19S, %12-15S"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_UQSHLL,
+ 0xea51010f, 0xfff1813f,
+ "uqshll%c\t%17-19l, %9-11h, %j"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_UQSHL,
+ 0xea500f0f, 0xfff08f3f,
+ "uqshl%c\t%16-19S, %j"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_URSHRL,
+ 0xea51011f, 0xfff1813f,
+ "urshrl%c\t%17-19l, %9-11h, %j"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
+ MVE_URSHR,
+ 0xea500f1f, 0xfff08f3f,
+ "urshr%c\t%16-19S, %j"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ MVE_CSINC,
+ 0xea509000, 0xfff0f000,
+ "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ MVE_CSINV,
+ 0xea50a000, 0xfff0f000,
+ "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ MVE_CSET,
+ 0xea5f900f, 0xfffff00f,
+ "cset\t%8-11S, %4-7C"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ MVE_CSETM,
+ 0xea5fa00f, 0xfffff00f,
+ "csetm\t%8-11S, %4-7C"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ MVE_CSEL,
+ 0xea508000, 0xfff0f000,
+ "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ MVE_CSNEG,
+ 0xea50b000, 0xfff0f000,
+ "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ MVE_CINC,
+ 0xea509000, 0xfff0f000,
+ "cinc\t%8-11S, %16-19Z, %4-7C"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ MVE_CINV,
+ 0xea50a000, 0xfff0f000,
+ "cinv\t%8-11S, %16-19Z, %4-7C"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ MVE_CNEG,
+ 0xea50b000, 0xfff0f000,
+ "cneg\t%8-11S, %16-19Z, %4-7C"},
+
{ARM_FEATURE_CORE_LOW (0),
MVE_NONE,
0x00000000, 0x00000000, 0}
{
/* ARM instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
+ 0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
+ 0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
0xe320f010, 0xffffffff, "esb"},
+ /* V8-R instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
+ 0xf57ff04c, 0xffffffff, "dfb"},
+
/* V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
0x0320f005, 0x0fffffff, "sevl"},
/* Defined in V8 but is in NOP space so available to all arch. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
+ 0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
/* CRC32 instructions. */
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
/* Privileged Access Never extension instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
- 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
+ 0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"},
/* Virtualization Extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
/* V7 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
- 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
+ 0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"},
/* ARM V6T2 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
+ 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"},
/* ARM Security extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
0x0320f004, 0x0fffffff, "sev%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
- 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
+ 0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"},
/* ARM V6 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
+ 0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
+ 0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
+ 0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
+ 0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
+ 0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
+ 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
+ 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
+ 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
+ 0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
+ 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
+ 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
+ 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
+ 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
+ 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
+ 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
+ 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
+ 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
+ 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
+ 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
+ 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
+ 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
+ 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
+ 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
+ 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
+ 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
+ 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
+ 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
+ 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
+ 0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
+ 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
+ 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
+ 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
+ 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
+ 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
+ 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
+ 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
+ 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
+ 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"},
/* V5J instruction. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
/* V5 Instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xe1200070, 0xfff000f0,
- "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
+ "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfa000000, 0xfe000000, "blx\t%B"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
/* ARM Instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
+ 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
+ 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
/* The rest. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
- 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
+ 0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
{ARM_FEATURE_CORE_LOW (0),
%c print the condition code
%C print the condition code, or "s" if not conditional
%x print warning if conditional an not at end of IT block"
- %X print "\t; unpredictable <IT:code>" if conditional
+ %X print "\t@ unpredictable <IT:code>" if conditional
%I print IT instruction suffix and operands
%W print Thumb Writeback indicator for LDMIA
%<bitfield>r print bitfield as an ARM register
/* ARM V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"},
/* ARM V6K no-argument instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
/* ARM V6. */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
/* ARM V4T ISA (Thumb v1). */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
+ 0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"},
/* Format 4. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
/* format 13 */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"},
/* format 5 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
+ 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
+ 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
/* format 8 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
/* format 1 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
+ 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
/* format 3 */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"},
/* format 6 */
/* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x4800, 0xF800,
- "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
+ "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"},
/* format 9 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
+ 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
+ 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
+ 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
+ 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
/* format 10 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
+ 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
+ 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
/* format 11 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
+ 0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
+ 0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
/* format 12 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
+ 0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
+ 0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"},
/* format 15 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
/* format 17 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
/* format 16 */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
/* format 18 */
%P print address for pli instruction.
%c print the condition code
%x print warning if conditional an not at end of IT block"
- %X print "\t; unpredictable <IT:code>" if conditional
+ %X print "\t@ unpredictable <IT:code>" if conditional
%<bitfield>d print bitfield in decimal
%<bitfield>D print bitfield plus one in decimal
makes heavy use of special-case bit patterns. */
static const struct opcode32 thumb32_opcodes[] =
{
+ /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
+ Identification Extension. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
+ {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
+ 0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf3af800f, 0xffffffff, "bti"},
+ {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
+ 0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
+ {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
+ 0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
+
/* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf02fc001, 0xfffff001, "le\t%P"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf00fc001, 0xfffff001, "le\tlr, %P"},
+ 0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
+ 0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
+ 0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
+ 0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
+ 0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
+ 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
+ 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xe89f0000, 0xffff2000, "clrm%c\t%n"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
+ /* V8-R instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
+ 0xf3bf8f4c, 0xffffffff, "dfb%c"},
+
/* CRC32 instructions. */
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
/* Speculation Barriers. */
/* V7 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
+ 0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
0xf3bf8f2f, 0xffffffff, "clrex%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
+ 0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
+ 0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
+ 0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
+ 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
+ 0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
+ 0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
+ 0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
+ 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
+ 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
+ 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
+ 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
- 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
+ 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
+ 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
+ 0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
- 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
+ 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe9400000, 0xff500000,
- "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
+ "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe9500000, 0xff500000,
- "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
+ "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe8600000, 0xff700000,
- "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
+ "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe8700000, 0xff700000,
- "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
+ "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
{ "reg-names-atpcs", N_("Select register names used in the ATPCS"),
{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
{ "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
- { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
+ { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
+ { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
};
static const char *const iwmmxt_wwnames[] =
struct vpt_block
{
/* Are we in a vpt block. */
- bfd_boolean in_vpt_block;
+ bool in_vpt_block;
/* Next predicate state if in vpt block. */
enum vpt_pred_state next_pred_state;
static struct vpt_block vpt_block_state =
{
- FALSE,
+ false,
PRED_NONE,
0,
0,
#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
#define arm_regnames regnames[regname_selected].reg_names
-static bfd_boolean force_thumb = FALSE;
+static bool force_thumb = false;
+static uint16_t cde_coprocs = 0;
/* Current IT instruction state. This contains the same state as the IT
bits in the CPSR. */
static void
mark_outside_vpt_block (void)
{
- vpt_block_state.in_vpt_block = FALSE;
+ vpt_block_state.in_vpt_block = false;
vpt_block_state.next_pred_state = PRED_NONE;
vpt_block_state.predicate_mask = 0;
vpt_block_state.current_insn_num = 0;
static void
mark_inside_vpt_block (long given)
{
- vpt_block_state.in_vpt_block = TRUE;
+ vpt_block_state.in_vpt_block = true;
vpt_block_state.next_pred_state = PRED_THEN;
vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
vpt_block_state.current_insn_num = 0;
}
static void
-arm_decode_shift (long given, fprintf_ftype func, void *stream,
- bfd_boolean print_shift)
+arm_decode_shift (long given, fprintf_styled_ftype func, void *stream,
+ bool print_shift)
{
- func (stream, "%s", arm_regnames[given & 0xf]);
+ func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]);
if ((given & 0xff0) != 0)
{
{
if (shift == 3)
{
- func (stream, ", rrx");
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "rrx");
return;
}
}
if (print_shift)
- func (stream, ", %s #%d", arm_shift[shift], amount);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]);
+ func (stream, dis_style_immediate, "#%d", amount);
+ }
else
- func (stream, ", #%d", amount);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%d", amount);
+ }
}
else if ((given & 0x80) == 0x80)
- func (stream, "\t; <illegal shifter operand>");
+ func (stream, dis_style_comment_start,
+ "\t@ <illegal shifter operand>");
else if (print_shift)
- func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
- arm_regnames[(given & 0xf00) >> 8]);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "%s ",
+ arm_shift[(given & 0x60) >> 5]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[(given & 0xf00) >> 8]);
+ }
else
- func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[(given & 0xf00) >> 8]);
+ }
}
}
/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
-static bfd_boolean
+static bool
is_mve_okay_in_it (enum mve_instructions matched_insn)
{
switch (matched_insn)
case MVE_VMOV2_VEC_LANE_TO_GP:
case MVE_VMOV2_GP_TO_VEC_LANE:
case MVE_VMOV_VEC_LANE_TO_GP:
- return TRUE;
+ case MVE_LSLL:
+ case MVE_LSLLI:
+ case MVE_LSRL:
+ case MVE_ASRL:
+ case MVE_ASRLI:
+ case MVE_SQRSHRL:
+ case MVE_SQRSHR:
+ case MVE_UQRSHL:
+ case MVE_UQRSHLL:
+ case MVE_UQSHL:
+ case MVE_UQSHLL:
+ case MVE_URSHRL:
+ case MVE_URSHR:
+ case MVE_SRSHRL:
+ case MVE_SRSHR:
+ case MVE_SQSHLL:
+ case MVE_SQSHL:
+ return true;
default:
- return FALSE;
+ return false;
}
}
-static bfd_boolean
+static bool
is_mve_architecture (struct disassemble_info *info)
{
struct arm_private_data *private_data = info->private_data;
if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
&& !ARM_CPU_IS_ANY (allowed_arches))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
is_vpt_instruction (long given)
{
/* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
if ((given & 0x0040e000) == 0)
- return FALSE;
+ return false;
/* VPT floating point T1 variant. */
if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
|| ((given & 0xff811f50) == 0xfe011f40)
/* VPST vector T variant. */
|| ((given & 0xffbf1fff) == 0xfe310f4d))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
This helps us decode instructions that change mnemonic depending on specific
operand values/encodings. */
-static bfd_boolean
+static bool
is_mve_encoding_conflict (unsigned long given,
enum mve_instructions matched_insn)
{
{
case MVE_VPST:
if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VPT_FP_T1:
if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
- return TRUE;
+ return true;
if ((arm_decode_field (given, 12, 12) == 0)
&& (arm_decode_field (given, 0, 0) == 1))
- return TRUE;
- return FALSE;
+ return true;
+ return false;
case MVE_VPT_FP_T2:
if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
- return TRUE;
+ return true;
if (arm_decode_field (given, 0, 3) == 0xd)
- return TRUE;
- return FALSE;
+ return true;
+ return false;
case MVE_VPT_VEC_T1:
case MVE_VPT_VEC_T2:
case MVE_VPT_VEC_T5:
case MVE_VPT_VEC_T6:
if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
- return TRUE;
+ return true;
if (arm_decode_field (given, 20, 21) == 3)
- return TRUE;
- return FALSE;
+ return true;
+ return false;
case MVE_VCMP_FP_T1:
if ((arm_decode_field (given, 12, 12) == 0)
&& (arm_decode_field (given, 0, 0) == 1))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VCMP_FP_T2:
if (arm_decode_field (given, 0, 3) == 0xd)
- return TRUE;
+ return true;
else
- return FALSE;
-
+ return false;
+
+ case MVE_VQADD_T2:
+ case MVE_VQSUB_T2:
+ case MVE_VMUL_VEC_T2:
+ case MVE_VMULH:
+ case MVE_VRMULH:
+ case MVE_VMLA:
+ case MVE_VMAX:
+ case MVE_VMIN:
+ case MVE_VBRSR:
case MVE_VADD_VEC_T2:
case MVE_VSUB_VEC_T2:
case MVE_VABAV:
case MVE_VCMP_VEC_T5:
case MVE_VCMP_VEC_T6:
if (arm_decode_field (given, 20, 21) == 3)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VLD2:
case MVE_VLD4:
case MVE_VST2:
case MVE_VST4:
if (arm_decode_field (given, 7, 8) == 3)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VSTRB_T1:
case MVE_VSTRH_T2:
if ((arm_decode_field (given, 24, 24) == 0)
&& (arm_decode_field (given, 21, 21) == 0))
{
- return TRUE;
+ return true;
}
else if ((arm_decode_field (given, 7, 8) == 3))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
+ case MVE_VLDRB_T1:
+ case MVE_VLDRH_T2:
+ case MVE_VLDRW_T7:
case MVE_VSTRB_T5:
case MVE_VSTRH_T6:
case MVE_VSTRW_T7:
if ((arm_decode_field (given, 24, 24) == 0)
&& (arm_decode_field (given, 21, 21) == 0))
{
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VCVT_FP_FIX_VEC:
return (arm_decode_field (given, 16, 21) & 0x38) == 0;
unsigned long cmode = arm_decode_field (given, 8, 11);
if ((cmode & 1) == 0)
- return TRUE;
+ return true;
else if ((cmode & 0xc) == 0xc)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
case MVE_VMVN_IMM:
{
unsigned long cmode = arm_decode_field (given, 8, 11);
- if ((cmode & 9) == 1)
- return TRUE;
- else if ((cmode & 5) == 1)
- return TRUE;
- else if ((cmode & 0xe) == 0xe)
- return TRUE;
+ if (cmode == 0xe)
+ return true;
+ else if ((cmode & 0x9) == 1)
+ return true;
+ else if ((cmode & 0xd) == 9)
+ return true;
else
- return FALSE;
+ return false;
}
case MVE_VMOV_IMM_TO_VEC:
if ((arm_decode_field (given, 5, 5) == 1)
&& (arm_decode_field (given, 8, 11) != 0xe))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VMOVL:
{
unsigned long size = arm_decode_field (given, 19, 20);
if ((size == 0) || (size == 3))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
+ case MVE_VMAXA:
+ case MVE_VMINA:
+ case MVE_VMAXV:
+ case MVE_VMAXAV:
+ case MVE_VMINV:
+ case MVE_VMINAV:
case MVE_VQRSHL_T2:
case MVE_VQSHL_T1:
case MVE_VRSHL_T2:
case MVE_VQMOVUN:
case MVE_VQMOVN:
if (arm_decode_field (given, 18, 19) == 3)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VMLSLDAV:
case MVE_VRMLSLDAVH:
case MVE_VMLALDAV:
case MVE_VADDLV:
if (arm_decode_field (given, 20, 22) == 7)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VRMLALDAVH:
if ((arm_decode_field (given, 20, 22) & 6) == 6)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VDWDUP:
case MVE_VIWDUP:
if ((arm_decode_field (given, 20, 21) == 3)
|| (arm_decode_field (given, 1, 3) == 7))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
case MVE_VSHLL_T1:
unsigned long sz = arm_decode_field (given, 19, 20);
if ((sz == 1) || (sz == 2))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
case MVE_VQSHL_T2:
case MVE_VQSHLU_T3:
case MVE_VSLI:
case MVE_VSRI:
if (arm_decode_field (given, 19, 21) == 0)
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
+
+ case MVE_VCTP:
+ if (arm_decode_field (given, 16, 19) == 0xf)
+ return true;
+ else
+ return false;
+
+ case MVE_ASRLI:
+ case MVE_ASRL:
+ case MVE_LSLLI:
+ case MVE_LSLL:
+ case MVE_LSRL:
+ case MVE_SQRSHRL:
+ case MVE_SQSHLL:
+ case MVE_SRSHRL:
+ case MVE_UQRSHLL:
+ case MVE_UQSHLL:
+ case MVE_URSHRL:
+ if (arm_decode_field (given, 9, 11) == 0x7)
+ return true;
+ else
+ return false;
+
+ case MVE_CSINC:
+ case MVE_CSINV:
+ {
+ unsigned long rm, rn;
+ rm = arm_decode_field (given, 0, 3);
+ rn = arm_decode_field (given, 16, 19);
+ /* CSET/CSETM. */
+ if (rm == 0xf && rn == 0xf)
+ return true;
+ /* CINC/CINV. */
+ else if (rn == rm && rn != 0xf)
+ return true;
+ }
+ /* Fall through. */
+ case MVE_CSEL:
+ case MVE_CSNEG:
+ if (arm_decode_field (given, 0, 3) == 0xd)
+ return true;
+ /* CNEG. */
+ else if (matched_insn == MVE_CSNEG)
+ if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
+ return true;
+ return false;
default:
case MVE_VADD_FP_T1:
case MVE_VADD_FP_T2:
case MVE_VADD_VEC_T1:
- return FALSE;
+ return false;
}
}
enum mve_instructions matched_insn)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
unsigned long p, w, gpr, imm, add, mod_imm;
else
add_sub = "-";
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s", arm_regnames[gpr]);
if (p == 1)
{
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
/* Offset mode. */
if (w == 0)
- func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
+ func (stream, dis_style_text, "]");
/* Pre-indexed mode. */
else
- func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
+ func (stream, dis_style_text, "]!");
}
else if ((p == 0) && (w == 1))
- /* Post-index mode. */
- func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
+ {
+ /* Post-index mode. */
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
+ }
}
/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
this encoding is undefined. */
-static bfd_boolean
+static bool
is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
enum mve_undefined *undefined_code)
{
if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
+ case MVE_VQADD_T1:
+ case MVE_VQSUB_T1:
+ case MVE_VMUL_VEC_T1:
case MVE_VABD_VEC:
case MVE_VADD_VEC_T1:
case MVE_VSUB_VEC_T1:
if (arm_decode_field (given, 20, 21) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VLDRB_T1:
if (arm_decode_field (given, 7, 8) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VLDRH_T2:
if (arm_decode_field (given, 7, 8) <= 1)
{
*undefined_code = UNDEF_SIZE_LE_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VSTRB_T1:
if ((arm_decode_field (given, 7, 8) == 0))
{
*undefined_code = UNDEF_SIZE_0;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VSTRH_T2:
if ((arm_decode_field (given, 7, 8) <= 1))
{
*undefined_code = UNDEF_SIZE_LE_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VLDRB_GATHER_T1:
if (arm_decode_field (given, 7, 8) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else if ((arm_decode_field (given, 28, 28) == 0)
&& (arm_decode_field (given, 7, 8) == 0))
{
*undefined_code = UNDEF_NOT_UNS_SIZE_0;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VLDRH_GATHER_T2:
if (arm_decode_field (given, 7, 8) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else if ((arm_decode_field (given, 28, 28) == 0)
&& (arm_decode_field (given, 7, 8) == 1))
{
*undefined_code = UNDEF_NOT_UNS_SIZE_1;
- return TRUE;
+ return true;
}
else if (arm_decode_field (given, 7, 8) == 0)
{
*undefined_code = UNDEF_SIZE_0;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VLDRW_GATHER_T3:
if (arm_decode_field (given, 7, 8) != 2)
{
*undefined_code = UNDEF_SIZE_NOT_2;
- return TRUE;
+ return true;
}
else if (arm_decode_field (given, 28, 28) == 0)
{
*undefined_code = UNDEF_NOT_UNSIGNED;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VLDRD_GATHER_T4:
if (arm_decode_field (given, 7, 8) != 3)
{
*undefined_code = UNDEF_SIZE_NOT_3;
- return TRUE;
+ return true;
}
else if (arm_decode_field (given, 28, 28) == 0)
{
*undefined_code = UNDEF_NOT_UNSIGNED;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VSTRB_SCATTER_T1:
if (arm_decode_field (given, 7, 8) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VSTRH_SCATTER_T2:
{
if (size == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else if (size == 0)
{
*undefined_code = UNDEF_SIZE_0;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VSTRW_SCATTER_T3:
if (arm_decode_field (given, 7, 8) != 2)
{
*undefined_code = UNDEF_SIZE_NOT_2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VSTRD_SCATTER_T4:
if (arm_decode_field (given, 7, 8) != 3)
{
*undefined_code = UNDEF_SIZE_NOT_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VCVT_FP_FIX_VEC:
{
if ((imm6 & 0x20) == 0)
{
*undefined_code = UNDEF_VCVT_IMM6;
- return TRUE;
+ return true;
}
if ((arm_decode_field (given, 9, 9) == 0)
&& ((imm6 & 0x30) == 0x20))
{
*undefined_code = UNDEF_VCVT_FSI_IMM6;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
+ case MVE_VNEG_FP:
case MVE_VABS_FP:
case MVE_VCVT_BETWEEN_FP_INT:
case MVE_VCVT_FROM_FP_TO_INT:
if (size == 0)
{
*undefined_code = UNDEF_SIZE_0;
- return TRUE;
+ return true;
}
else if (size == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VMOV_VEC_LANE_TO_GP:
if ((op1 == 0) || (op1 == 1))
{
*undefined_code = UNDEF_BAD_U_OP1_OP2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
else if (op2 == 2)
{
if ((op1 == 0) || (op1 == 1))
{
*undefined_code = UNDEF_BAD_OP1_OP2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
- return FALSE;
+ return false;
}
case MVE_VMOV_GP_TO_VEC_LANE:
if ((op1 == 0) || (op1 == 1))
{
*undefined_code = UNDEF_BAD_OP1_OP2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
+
+ case MVE_VMOV_VEC_TO_VEC:
+ if ((arm_decode_field (given, 5, 5) == 1)
+ || (arm_decode_field (given, 22, 22) == 1))
+ return true;
+ return false;
case MVE_VMOV_IMM_TO_VEC:
if (arm_decode_field (given, 5, 5) == 0)
if (((cmode & 9) == 1) || ((cmode & 5) == 1))
{
*undefined_code = UNDEF_OP_0_BAD_CMODE;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
case MVE_VSHLL_T2:
case MVE_VMOVN:
if (arm_decode_field (given, 18, 19) == 2)
{
*undefined_code = UNDEF_SIZE_2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VRMLALDAVH:
case MVE_VMLADAV_T1:
&& (arm_decode_field (given, 12, 12) == 1))
{
*undefined_code = UNDEF_XCHG_UNS;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VQSHRN:
case MVE_VQSHRUN:
{
unsigned long sz = arm_decode_field (given, 19, 20);
if (sz == 1)
- return FALSE;
+ return false;
else if ((sz & 2) == 2)
- return FALSE;
+ return false;
else
{
*undefined_code = UNDEF_SIZE;
- return TRUE;
+ return true;
}
}
break;
{
unsigned long sz = arm_decode_field (given, 19, 21);
if ((sz & 7) == 1)
- return FALSE;
+ return false;
else if ((sz & 6) == 2)
- return FALSE;
+ return false;
else if ((sz & 4) == 4)
- return FALSE;
+ return false;
else
{
*undefined_code = UNDEF_SIZE;
- return TRUE;
+ return true;
}
}
if (arm_decode_field (given, 19, 20) == 0)
{
*undefined_code = UNDEF_SIZE_0;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VABS_VEC:
if (arm_decode_field (given, 18, 19) == 3)
{
*undefined_code = UNDEF_SIZE_3;
- return TRUE;
+ return true;
+ }
+ else
+ return false;
+
+ case MVE_VQNEG:
+ case MVE_VQABS:
+ case MVE_VNEG_VEC:
+ case MVE_VCLS:
+ case MVE_VCLZ:
+ if (arm_decode_field (given, 18, 19) == 3)
+ {
+ *undefined_code = UNDEF_SIZE_3;
+ return true;
+ }
+ else
+ return false;
+
+ case MVE_VREV16:
+ if (arm_decode_field (given, 18, 19) == 0)
+ return false;
+ else
+ {
+ *undefined_code = UNDEF_SIZE_NOT_0;
+ return true;
}
+
+ case MVE_VREV32:
+ {
+ unsigned long size = arm_decode_field (given, 18, 19);
+ if ((size & 2) == 2)
+ {
+ *undefined_code = UNDEF_SIZE_2;
+ return true;
+ }
else
- return FALSE;
+ return false;
+ }
+
+ case MVE_VREV64:
+ if (arm_decode_field (given, 18, 19) != 3)
+ return false;
+ else
+ {
+ *undefined_code = UNDEF_SIZE_3;
+ return true;
+ }
default:
- return FALSE;
+ return false;
}
}
Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
why this encoding is unpredictable. */
-static bfd_boolean
+static bool
is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
enum mve_unpredictable *unpredictable_code)
{
&& (arm_decode_field (given, 5, 5) == 1))
{
*unpredictable_code = UNPRED_FCA_0_FCB_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VPT_VEC_T4:
case MVE_VPT_VEC_T5:
if (arm_decode_field (given, 0, 3) == 0xd)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VDUP:
{
if (gpr == 0xd)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else if (gpr == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
+ case MVE_VQADD_T2:
+ case MVE_VQSUB_T2:
+ case MVE_VMUL_FP_T2:
+ case MVE_VMUL_VEC_T2:
+ case MVE_VMLA:
+ case MVE_VBRSR:
case MVE_VADD_FP_T2:
case MVE_VSUB_FP_T2:
case MVE_VADD_VEC_T2:
if (gpr == 0xd)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else if (gpr == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
case MVE_VLD2:
if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
{
*unpredictable_code = UNPRED_R13_AND_WB;
- return TRUE;
+ return true;
}
if (rn == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
{
*unpredictable_code = UNPRED_Q_GT_6;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VLD4:
if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
{
*unpredictable_code = UNPRED_R13_AND_WB;
- return TRUE;
+ return true;
}
if (rn == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
{
*unpredictable_code = UNPRED_Q_GT_4;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VLDRB_T5:
if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
{
*unpredictable_code = UNPRED_R13_AND_WB;
- return TRUE;
+ return true;
}
else if (rn == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VLDRB_GATHER_T1:
if (arm_decode_field (given, 0, 0) == 1)
{
*unpredictable_code = UNPRED_OS;
- return TRUE;
+ return true;
}
/* fall through. */
if (qd == qm)
{
*unpredictable_code = UNPRED_Q_REGS_EQUAL;
- return TRUE;
+ return true;
}
if (arm_decode_field (given, 16, 19) == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
case MVE_VLDRW_GATHER_T5:
if (qd == qm)
{
*unpredictable_code = UNPRED_Q_REGS_EQUAL;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VSTRB_SCATTER_T1:
if (arm_decode_field (given, 16, 19) == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
else if (arm_decode_field (given, 0, 0) == 1)
{
*unpredictable_code = UNPRED_OS;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VSTRH_SCATTER_T2:
case MVE_VSTRW_SCATTER_T3:
if (arm_decode_field (given, 16, 19) == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VMOV2_VEC_LANE_TO_GP:
case MVE_VMOV2_GP_TO_VEC_LANE:
if ((rt == 0xd) || (rt2 == 0xd))
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else if ((rt == 0xf) || (rt2 == 0xf))
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
- else if (rt == rt2)
+ else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
{
*unpredictable_code = UNPRED_GP_REGS_EQUAL;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
+ case MVE_VMAXV:
+ case MVE_VMAXAV:
+ case MVE_VMAXNMV_FP:
+ case MVE_VMAXNMAV_FP:
+ case MVE_VMINNMV_FP:
+ case MVE_VMINNMAV_FP:
+ case MVE_VMINV:
+ case MVE_VMINAV:
case MVE_VABAV:
case MVE_VMOV_HFP_TO_GP:
case MVE_VMOV_GP_TO_VEC_LANE:
if (rda == 0xd)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else if (rda == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
- case MVE_VQRDMLADH:
- case MVE_VQDMLSDH:
- case MVE_VQRDMLSDH:
- case MVE_VQDMLADH:
case MVE_VMULL_INT:
{
unsigned long Qd;
if ((Qd == Qn) || (Qd == Qm))
{
*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
}
case MVE_VCMUL_FP:
if ((Qd == Qn) || (Qd == Qm))
{
*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
}
case MVE_VQDMULL_T2:
if (gpr == 0xd)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else if (gpr == 0xf)
{
*unpredictable_code = UNPRED_R15;
- return TRUE;
+ return true;
}
if (arm_decode_field (given, 28, 28) == 1)
= arm_decode_field_multiple (given, 13, 15, 22, 22);
unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
- if ((Qd == Qn))
+ if (Qd == Qn)
{
*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
- return FALSE;
+ return false;
}
case MVE_VMLSLDAV:
if (arm_decode_field (given, 20, 22) == 6)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VDWDUP:
case MVE_VIWDUP:
if (arm_decode_field (given, 1, 3) == 6)
{
*unpredictable_code = UNPRED_R13;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case MVE_VCADD_VEC:
case MVE_VHCADD:
if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
{
*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VCADD_FP:
if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
{
*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case MVE_VCMLA_FP:
if ((Qda == Qn) || (Qda == Qm))
{
*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
+ }
+ else
+ return false;
+
+ }
+
+ case MVE_VCTP:
+ if (arm_decode_field (given, 16, 19) == 0xd)
+ {
+ *unpredictable_code = UNPRED_R13;
+ return true;
+ }
+ else
+ return false;
+
+ case MVE_VREV64:
+ {
+ unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
+ unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
+
+ if (qd == qm)
+ {
+ *unpredictable_code = UNPRED_Q_REGS_EQUAL;
+ return true;
}
else
- return FALSE;
+ return false;
+ }
+
+ case MVE_LSLL:
+ case MVE_LSLLI:
+ case MVE_LSRL:
+ case MVE_ASRL:
+ case MVE_ASRLI:
+ case MVE_UQSHLL:
+ case MVE_UQRSHLL:
+ case MVE_URSHRL:
+ case MVE_SRSHRL:
+ case MVE_SQSHLL:
+ case MVE_SQRSHRL:
+ {
+ unsigned long gpr = arm_decode_field (given, 9, 11);
+ gpr = ((gpr << 1) | 1);
+ if (gpr == 0xd)
+ {
+ *unpredictable_code = UNPRED_R13;
+ return true;
+ }
+ else if (gpr == 0xf)
+ {
+ *unpredictable_code = UNPRED_R15;
+ return true;
+ }
+ return false;
}
default:
- return FALSE;
+ return false;
}
}
unsigned long op1 = arm_decode_field (given, 21, 22);
unsigned long op2 = arm_decode_field (given, 5, 6);
unsigned long h = arm_decode_field (given, 16, 16);
- unsigned long index, esize, targetBeat, idx;
+ unsigned long index_operand, esize, targetBeat, idx;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
if ((op1 & 0x2) == 0x2)
{
- index = op2;
+ index_operand = op2;
esize = 8;
}
else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
{
- index = op2 >> 1;
+ index_operand = op2 >> 1;
esize = 16;
}
else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
{
- index = 0;
+ index_operand = 0;
esize = 32;
}
else
{
- func (stream, "<undefined index>");
+ func (stream, dis_style_text, "<undefined index>");
return;
}
targetBeat = (op1 & 0x1) | (h << 1);
- idx = index + targetBeat * (32/esize);
+ idx = index_operand + targetBeat * (32/esize);
- func (stream, "%lu", idx);
+ func (stream, dis_style_immediate, "%lu", idx);
}
/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
int size = 0;
int isfloat = 0;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
/* On Neon the 'i' bit is at bit 24, on mve it is
at bit 28. */
}
else
{
- func (stream, "<illegal constant %.8x:%x:%x>",
+ func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>",
bits, cmode, op);
size = 32;
return;
}
- // printU determines whether the immediate value should be printed as
- // unsigned.
+ /* printU determines whether the immediate value should be printed as
+ unsigned. */
unsigned printU = 0;
switch (insn->mve_op)
{
default:
break;
- // We want this for instructions that don't have a 'signed' type
+ /* We want this for instructions that don't have a 'signed' type. */
case MVE_VBIC_IMM:
case MVE_VORR_IMM:
case MVE_VMVN_IMM:
switch (size)
{
case 8:
- func (stream, "#%ld\t; 0x%.2lx", value, value);
+ func (stream, dis_style_immediate, "#%ld", value);
+ func (stream, dis_style_comment_start, "\t@ 0x%.2lx", value);
break;
case 16:
- func (stream,
- printU
- ? "#%lu\t; 0x%.4lx"
- : "#%ld\t; 0x%.4lx", value, value);
+ func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value);
+ func (stream, dis_style_comment_start, "\t@ 0x%.4lx", value);
break;
case 32:
(& floatformat_ieee_single_little, valbytes,
& fvalue);
- func (stream, "#%.7g\t; 0x%.8lx", fvalue,
- value);
+ func (stream, dis_style_immediate, "#%.7g", fvalue);
+ func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
}
else
- func (stream,
- printU
- ? "#%lu\t; 0x%.8lx"
- : "#%ld\t; 0x%.8lx",
- (long) (((value & 0x80000000L) != 0)
- && !printU
- ? value | ~0xffffffffL : value),
- value);
+ {
+ func (stream, dis_style_immediate,
+ printU ? "#%lu" : "#%ld",
+ (long) (((value & 0x80000000L) != 0)
+ && !printU
+ ? value | ~0xffffffffL : value));
+ func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
+ }
break;
case 64:
- func (stream, "#0x%.8lx%.8lx", hival, value);
+ func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value);
break;
default:
enum mve_undefined undefined_code)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
-
- func (stream, "\t\tundefined instruction: ");
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ /* Initialize REASON to avoid compiler warning about uninitialized
+ usage, though such usage should be impossible. */
+ const char *reason = "??";
switch (undefined_code)
{
case UNDEF_SIZE:
- func (stream, "illegal size");
+ reason = "illegal size";
break;
case UNDEF_SIZE_0:
- func (stream, "size equals zero");
+ reason = "size equals zero";
break;
case UNDEF_SIZE_2:
- func (stream, "size equals two");
+ reason = "size equals two";
break;
case UNDEF_SIZE_3:
- func (stream, "size equals three");
+ reason = "size equals three";
break;
case UNDEF_SIZE_LE_1:
- func (stream, "size <= 1");
+ reason = "size <= 1";
+ break;
+
+ case UNDEF_SIZE_NOT_0:
+ reason = "size not equal to 0";
break;
case UNDEF_SIZE_NOT_2:
- func (stream, "size not equal to 2");
+ reason = "size not equal to 2";
break;
case UNDEF_SIZE_NOT_3:
- func (stream, "size not equal to 3");
+ reason = "size not equal to 3";
break;
case UNDEF_NOT_UNS_SIZE_0:
- func (stream, "not unsigned and size = zero");
+ reason = "not unsigned and size = zero";
break;
case UNDEF_NOT_UNS_SIZE_1:
- func (stream, "not unsigned and size = one");
+ reason = "not unsigned and size = one";
break;
case UNDEF_NOT_UNSIGNED:
- func (stream, "not unsigned");
+ reason = "not unsigned";
break;
case UNDEF_VCVT_IMM6:
- func (stream, "invalid imm6");
+ reason = "invalid imm6";
break;
case UNDEF_VCVT_FSI_IMM6:
- func (stream, "fsi = 0 and invalid imm6");
+ reason = "fsi = 0 and invalid imm6";
break;
case UNDEF_BAD_OP1_OP2:
- func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
+ reason = "bad size with op2 = 2 and op1 = 0 or 1";
break;
case UNDEF_BAD_U_OP1_OP2:
- func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
+ reason = "unsigned with op2 = 0 and op1 = 0 or 1";
break;
case UNDEF_OP_0_BAD_CMODE:
- func (stream, "op field equal 0 and bad cmode");
+ reason = "op field equal 0 and bad cmode";
break;
case UNDEF_XCHG_UNS:
- func (stream, "exchange and unsigned together");
+ reason = "exchange and unsigned together";
break;
case UNDEF_NONE:
+ reason = "";
break;
}
+ func (stream, dis_style_text, "\t\tundefined instruction: %s", reason);
}
static void
enum mve_unpredictable unpredict_code)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
-
- func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ /* Initialize REASON to avoid compiler warning about uninitialized
+ usage, though such usage should be impossible. */
+ const char *reason = "??";
switch (unpredict_code)
{
case UNPRED_IT_BLOCK:
- func (stream, "mve instruction in it block");
+ reason = "mve instruction in it block";
break;
case UNPRED_FCA_0_FCB_1:
- func (stream, "condition bits, fca = 0 and fcb = 1");
+ reason = "condition bits, fca = 0 and fcb = 1";
break;
case UNPRED_R13:
- func (stream, "use of r13 (sp)");
+ reason = "use of r13 (sp)";
break;
case UNPRED_R15:
- func (stream, "use of r15 (pc)");
+ reason = "use of r15 (pc)";
break;
case UNPRED_Q_GT_4:
- func (stream, "start register block > r4");
+ reason = "start register block > r4";
break;
case UNPRED_Q_GT_6:
- func (stream, "start register block > r6");
+ reason = "start register block > r6";
break;
case UNPRED_R13_AND_WB:
- func (stream, "use of r13 and write back");
+ reason = "use of r13 and write back";
break;
case UNPRED_Q_REGS_EQUAL:
- func (stream,
- "same vector register used for destination and other operand");
+ reason = "same vector register used for destination and other operand";
break;
case UNPRED_OS:
- func (stream, "use of offset scaled");
+ reason = "use of offset scaled";
break;
case UNPRED_GP_REGS_EQUAL:
- func (stream, "same general-purpose register used for both operands");
+ reason = "same general-purpose register used for both operands";
break;
case UNPRED_Q_REGS_EQ_AND_SIZE_1:
- func (stream, "use of identical q registers and size = 1");
+ reason = "use of identical q registers and size = 1";
break;
case UNPRED_Q_REGS_EQ_AND_SIZE_2:
- func (stream, "use of identical q registers and size = 1");
+ reason = "use of identical q registers and size = 1";
break;
case UNPRED_NONE:
+ reason = "";
break;
}
+
+ func (stream, dis_style_comment_start, "%s: %s",
+ UNPREDICTABLE_INSTRUCTION, reason);
}
/* Print register block operand for mve vld2/vld4/vst2/vld4. */
enum mve_instructions matched_insn)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
unsigned long q_reg_start = arm_decode_field_multiple (given,
13, 15,
case MVE_VLD2:
case MVE_VST2:
if (q_reg_start <= 6)
- func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
+ {
+ func (stream, dis_style_text, "{");
+ func (stream, dis_style_register, "q%ld", q_reg_start);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "q%ld", q_reg_start + 1);
+ func (stream, dis_style_text, "}");
+ }
else
- func (stream, "<illegal reg q%ld>", q_reg_start);
+ func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
break;
case MVE_VLD4:
case MVE_VST4:
if (q_reg_start <= 4)
- func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
- q_reg_start + 1, q_reg_start + 2,
- q_reg_start + 3);
+ {
+ func (stream, dis_style_text, "{");
+ func (stream, dis_style_register, "q%ld", q_reg_start);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "q%ld", q_reg_start + 1);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "q%ld", q_reg_start + 2);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "q%ld", q_reg_start + 3);
+ func (stream, dis_style_text, "}");
+ }
else
- func (stream, "<illegal reg q%ld>", q_reg_start);
+ func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
break;
default:
enum mve_instructions matched_insn)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
switch (matched_insn)
{
switch (arm_decode_field (given, 8, 9))
{
case 0:
- func (stream, "a");
+ func (stream, dis_style_mnemonic, "a");
break;
case 1:
- func (stream, "n");
+ func (stream, dis_style_mnemonic, "n");
break;
case 2:
- func (stream, "p");
+ func (stream, dis_style_mnemonic, "p");
break;
case 3:
- func (stream, "m");
+ func (stream, dis_style_mnemonic, "m");
break;
default:
switch (arm_decode_field (given, 7, 9))
{
case 0:
- func (stream, "n");
+ func (stream, dis_style_mnemonic, "n");
break;
case 1:
- func (stream, "x");
+ func (stream, dis_style_mnemonic, "x");
break;
case 2:
- func (stream, "a");
+ func (stream, dis_style_mnemonic, "a");
break;
case 3:
- func (stream, "z");
+ func (stream, dis_style_mnemonic, "z");
break;
case 5:
- func (stream, "m");
+ func (stream, dis_style_mnemonic, "m");
break;
case 7:
- func (stream, "p");
+ func (stream, dis_style_mnemonic, "p");
case 4:
case 6:
{
unsigned long mode = 0;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
switch (matched_insn)
{
switch (mode)
{
case 0:
- func (stream, "f16.s16");
+ func (stream, dis_style_mnemonic, "f16.s16");
break;
case 1:
- func (stream, "s16.f16");
+ func (stream, dis_style_mnemonic, "s16.f16");
break;
case 2:
- func (stream, "f16.u16");
+ func (stream, dis_style_mnemonic, "f16.u16");
break;
case 3:
- func (stream, "u16.f16");
+ func (stream, dis_style_mnemonic, "u16.f16");
break;
case 4:
- func (stream, "f32.s32");
+ func (stream, dis_style_mnemonic, "f32.s32");
break;
case 5:
- func (stream, "s32.f32");
+ func (stream, dis_style_mnemonic, "s32.f32");
break;
case 6:
- func (stream, "f32.u32");
+ func (stream, dis_style_mnemonic, "f32.u32");
break;
case 7:
- func (stream, "u32.f32");
+ func (stream, dis_style_mnemonic, "u32.f32");
break;
default:
switch (op)
{
case 0:
- func (stream, "f16.s16");
+ func (stream, dis_style_mnemonic, "f16.s16");
break;
case 1:
- func (stream, "f16.u16");
+ func (stream, dis_style_mnemonic, "f16.u16");
break;
case 2:
- func (stream, "s16.f16");
+ func (stream, dis_style_mnemonic, "s16.f16");
break;
case 3:
- func (stream, "u16.f16");
+ func (stream, dis_style_mnemonic, "u16.f16");
break;
default:
switch (op)
{
case 0:
- func (stream, "f32.s32");
+ func (stream, dis_style_mnemonic, "f32.s32");
break;
case 1:
- func (stream, "f32.u32");
+ func (stream, dis_style_mnemonic, "f32.u32");
break;
case 2:
- func (stream, "s32.f32");
+ func (stream, dis_style_mnemonic, "s32.f32");
break;
case 3:
- func (stream, "u32.f32");
+ func (stream, dis_style_mnemonic, "u32.f32");
break;
}
}
{
unsigned long op = arm_decode_field (given, 28, 28);
if (op == 0)
- func (stream, "f16.f32");
+ func (stream, dis_style_mnemonic, "f16.f32");
else if (op == 1)
- func (stream, "f32.f16");
+ func (stream, dis_style_mnemonic, "f32.f16");
}
break;
switch (size)
{
case 2:
- func (stream, "s16.f16");
+ func (stream, dis_style_mnemonic, "s16.f16");
break;
case 3:
- func (stream, "u16.f16");
+ func (stream, dis_style_mnemonic, "u16.f16");
break;
case 4:
- func (stream, "s32.f32");
+ func (stream, dis_style_mnemonic, "s32.f32");
break;
case 5:
- func (stream, "u32.f32");
+ func (stream, dis_style_mnemonic, "u32.f32");
break;
default:
unsigned long rot_width)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
if (rot_width == 1)
{
switch (rot)
{
case 0:
- func (stream, "90");
+ func (stream, dis_style_immediate, "90");
break;
case 1:
- func (stream, "270");
+ func (stream, dis_style_immediate, "270");
break;
default:
break;
switch (rot)
{
case 0:
- func (stream, "0");
+ func (stream, dis_style_immediate, "0");
break;
case 1:
- func (stream, "90");
+ func (stream, dis_style_immediate, "90");
break;
case 2:
- func (stream, "180");
+ func (stream, dis_style_immediate, "180");
break;
case 3:
- func (stream, "270");
+ func (stream, dis_style_immediate, "270");
break;
default:
break;
print_instruction_predicate (struct disassemble_info *info)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
if (vpt_block_state.next_pred_state == PRED_THEN)
- func (stream, "t");
+ func (stream, dis_style_mnemonic, "t");
else if (vpt_block_state.next_pred_state == PRED_ELSE)
- func (stream, "e");
+ func (stream, dis_style_mnemonic, "e");
}
static void
enum mve_instructions matched_insn)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
switch (matched_insn)
{
case MVE_VADD_VEC_T1:
case MVE_VADD_VEC_T2:
case MVE_VADDV:
+ case MVE_VBRSR:
case MVE_VCADD_VEC:
+ case MVE_VCLS:
+ case MVE_VCLZ:
case MVE_VCMP_VEC_T1:
case MVE_VCMP_VEC_T2:
case MVE_VCMP_VEC_T3:
case MVE_VCMP_VEC_T4:
case MVE_VCMP_VEC_T5:
case MVE_VCMP_VEC_T6:
+ case MVE_VCTP:
case MVE_VDDUP:
case MVE_VDWDUP:
case MVE_VHADD_T1:
case MVE_VLDRD_GATHER_T4:
case MVE_VLDRB_T1:
case MVE_VLDRH_T2:
+ case MVE_VMAX:
+ case MVE_VMAXA:
+ case MVE_VMAXV:
+ case MVE_VMAXAV:
+ case MVE_VMIN:
+ case MVE_VMINA:
+ case MVE_VMINV:
+ case MVE_VMINAV:
+ case MVE_VMLA:
case MVE_VMLAS:
+ case MVE_VMUL_VEC_T1:
+ case MVE_VMUL_VEC_T2:
+ case MVE_VMULH:
+ case MVE_VRMULH:
+ case MVE_VMULL_INT:
+ case MVE_VNEG_FP:
+ case MVE_VNEG_VEC:
case MVE_VPT_VEC_T1:
case MVE_VPT_VEC_T2:
case MVE_VPT_VEC_T3:
case MVE_VPT_VEC_T4:
case MVE_VPT_VEC_T5:
case MVE_VPT_VEC_T6:
+ case MVE_VQABS:
+ case MVE_VQADD_T1:
+ case MVE_VQADD_T2:
case MVE_VQDMLADH:
case MVE_VQRDMLADH:
case MVE_VQDMLAH:
case MVE_VQRDMULH_T2:
case MVE_VQDMULH_T3:
case MVE_VQRDMULH_T4:
+ case MVE_VQNEG:
case MVE_VQRSHL_T1:
case MVE_VQRSHL_T2:
case MVE_VQSHL_T1:
case MVE_VQSHL_T4:
+ case MVE_VQSUB_T1:
+ case MVE_VQSUB_T2:
+ case MVE_VREV32:
+ case MVE_VREV64:
case MVE_VRHADD:
case MVE_VRINT_FP:
case MVE_VRSHL_T1:
case MVE_VSUB_VEC_T1:
case MVE_VSUB_VEC_T2:
if (size <= 3)
- func (stream, "%s", mve_vec_sizename[size]);
+ func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]);
else
- func (stream, "<undef size>");
+ func (stream, dis_style_text, "<undef size>");
break;
case MVE_VABD_FP:
case MVE_VFMA_FP:
case MVE_VFMS_FP:
case MVE_VFMAS_FP_SCALAR:
+ case MVE_VMAXNM_FP:
+ case MVE_VMAXNMA_FP:
+ case MVE_VMAXNMV_FP:
+ case MVE_VMAXNMAV_FP:
+ case MVE_VMINNM_FP:
+ case MVE_VMINNMA_FP:
+ case MVE_VMINNMV_FP:
+ case MVE_VMINNMAV_FP:
+ case MVE_VMUL_FP_T1:
+ case MVE_VMUL_FP_T2:
case MVE_VPT_FP_T1:
case MVE_VPT_FP_T2:
if (size == 0)
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
else if (size == 1)
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
case MVE_VCADD_FP:
case MVE_VQMOVN:
case MVE_VQMOVUN:
if (size == 0)
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
else if (size == 1)
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
case MVE_VMOVL:
if (size == 1)
- func (stream, "8");
+ func (stream, dis_style_mnemonic, "8");
else if (size == 2)
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
case MVE_VDUP:
switch (size)
{
case 0:
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
case 1:
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
case 2:
- func (stream, "8");
+ func (stream, dis_style_mnemonic, "8");
break;
default:
break;
switch (size)
{
case 0: case 4:
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
case 1: case 3:
case 5: case 7:
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
case 8: case 9: case 10: case 11:
case 12: case 13: case 14: case 15:
- func (stream, "8");
+ func (stream, dis_style_mnemonic, "8");
break;
default:
{
case 0: case 4: case 8:
case 12: case 24: case 26:
- func (stream, "i32");
+ func (stream, dis_style_mnemonic, "i32");
break;
case 16: case 20:
- func (stream, "i16");
+ func (stream, dis_style_mnemonic, "i16");
break;
case 28:
- func (stream, "i8");
+ func (stream, dis_style_mnemonic, "i8");
break;
case 29:
- func (stream, "i64");
+ func (stream, dis_style_mnemonic, "i64");
break;
case 30:
- func (stream, "f32");
+ func (stream, dis_style_mnemonic, "f32");
break;
default:
break;
case MVE_VMULL_POLY:
if (size == 0)
- func (stream, "p8");
+ func (stream, dis_style_mnemonic, "p8");
else if (size == 1)
- func (stream, "p16");
+ func (stream, dis_style_mnemonic, "p16");
break;
case MVE_VMVN_IMM:
{
case 0: case 2: case 4:
case 6: case 12: case 13:
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
case 8: case 10:
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
default:
{
case 1: case 3:
case 5: case 7:
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
case 9: case 11:
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
default:
switch (size)
{
case 1:
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
case 2: case 3:
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
default:
switch (size)
{
case 1:
- func (stream, "8");
+ func (stream, dis_style_mnemonic, "8");
break;
case 2: case 3:
- func (stream, "16");
+ func (stream, dis_style_mnemonic, "16");
break;
case 4: case 5: case 6: case 7:
- func (stream, "32");
+ func (stream, dis_style_mnemonic, "32");
break;
default:
enum mve_instructions matched_insn)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
int startAt0
= matched_insn == MVE_VQSHL_T2
else
print_mve_undefined (info, UNDEF_SIZE_0);
- func (stream, "%u", shiftAmount);
+ func (stream, dis_style_immediate, "%u", shiftAmount);
}
static void
enum mve_instructions matched_insn)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
long vec_cond = 0;
switch (matched_insn)
vec_cond = (((given & 0x1000) >> 10)
| ((given & 1) << 1)
| ((given & 0x0080) >> 7));
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_FP_T2:
vec_cond = (((given & 0x1000) >> 10)
| ((given & 0x0020) >> 4)
| ((given & 0x0080) >> 7));
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_VEC_T1:
case MVE_VCMP_VEC_T1:
vec_cond = (given & 0x0080) >> 7;
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_VEC_T2:
case MVE_VCMP_VEC_T2:
vec_cond = 2 | ((given & 0x0080) >> 7);
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_VEC_T3:
case MVE_VCMP_VEC_T3:
vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_VEC_T4:
case MVE_VCMP_VEC_T4:
vec_cond = (given & 0x0080) >> 7;
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_VEC_T5:
case MVE_VCMP_VEC_T5:
vec_cond = 2 | ((given & 0x0080) >> 7);
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_VPT_VEC_T6:
case MVE_VCMP_VEC_T6:
vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
- func (stream, "%s",vec_condnames[vec_cond]);
+ func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
break;
case MVE_NONE:
#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
#define PRE_BIT_SET (given & (1 << P_BIT))
+/* The assembler string for an instruction can include %{X:...%} patterns,
+ where the 'X' is one of the characters understood by this function.
+
+ This function takes the X character, and returns a new style. This new
+ style will be used by the caller to temporarily change the current base
+ style. */
+
+static enum disassembler_style
+decode_base_style (const char x)
+{
+ switch (x)
+ {
+ case 'A': return dis_style_address;
+ case 'B': return dis_style_sub_mnemonic;
+ case 'C': return dis_style_comment_start;
+ case 'D': return dis_style_assembler_directive;
+ case 'I': return dis_style_immediate;
+ case 'M': return dis_style_mnemonic;
+ case 'O': return dis_style_address_offset;
+ case 'R': return dis_style_register;
+ case 'S': return dis_style_symbol;
+ case 'T': return dis_style_text;
+ default:
+ abort ();
+ }
+}
/* Print one coprocessor instruction on INFO->STREAM.
Return TRUE if the instuction matched, FALSE if this is not a
recognised coprocessor instruction. */
-static bfd_boolean
-print_insn_coprocessor (bfd_vma pc,
- struct disassemble_info *info,
- long given,
- bfd_boolean thumb)
+static bool
+print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
+ bfd_vma pc,
+ struct disassemble_info *info,
+ long given,
+ bool thumb)
{
const struct sopcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
unsigned long mask;
unsigned long value = 0;
int cond;
arm_feature_set allowed_arches = ARM_ARCH_NONE;
arm_feature_set arm_ext_v8_1m_main =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
allowed_arches = private_data->features;
- for (insn = coprocessor_opcodes; insn->assembler; insn++)
+ for (insn = opcodes; insn->assembler; insn++)
{
unsigned long u_reg = 16;
- bfd_boolean is_unpredictable = FALSE;
+ bool is_unpredictable = false;
signed long value_in_comment = 0;
const char *c;
|| insn->value == 0xfc000000) /* stc2 */
{
if (cp_num == 9 || cp_num == 10 || cp_num == 11)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Armv8.1-M Mainline FP & MVE instructions. */
if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
if (*c == '%')
{
const char mod = *++c;
+
switch (mod)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case 'A':
if (mod == 'K')
offset = given & 0x7f;
- func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s",
+ arm_regnames [(given >> 16) & 0xf]);
if (PRE_BIT_SET || WRITEBACK_BIT_SET)
{
if (PRE_BIT_SET)
{
if (offset)
- func (stream, ", #%d]%s",
- (int) offset,
- WRITEBACK_BIT_SET ? "!" : "");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%d",
+ (int) offset);
+ func (stream, dis_style_text, "]%s",
+ WRITEBACK_BIT_SET ? "!" : "");
+ }
else if (NEGATIVE_BIT_SET)
- func (stream, ", #-0]");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#-0");
+ func (stream, dis_style_text, "]");
+ }
else
- func (stream, "]");
+ func (stream, dis_style_text, "]");
}
else
{
- func (stream, "]");
+ func (stream, dis_style_text, "]");
if (WRITEBACK_BIT_SET)
{
if (offset)
- func (stream, ", #%d", (int) offset);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate,
+ "#%d", (int) offset);
+ }
else if (NEGATIVE_BIT_SET)
- func (stream, ", #-0");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#-0");
+ }
}
else
{
- func (stream, ", {%s%d}",
+ func (stream, dis_style_text, ", {");
+ func (stream, dis_style_immediate, "%s%d",
(NEGATIVE_BIT_SET && !offset) ? "-" : "",
(int) offset);
+ func (stream, dis_style_text, "}");
value_in_comment = offset;
}
}
if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
{
- func (stream, "\t; ");
+ func (stream, dis_style_comment_start, "\t@ ");
/* For unaligned PCs, apply off-by-alignment
correction. */
info->print_address_func (offset + pc
int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
int offset = (given >> 1) & 0x3f;
+ func (stream, dis_style_text, "{");
if (offset == 1)
- func (stream, "{d%d}", regno);
+ func (stream, dis_style_register, "d%d", regno);
else if (regno + offset > 32)
- func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
+ {
+ func (stream, dis_style_register, "d%d", regno);
+ func (stream, dis_style_text, "-<overflow reg d%d>",
+ regno + offset - 1);
+ }
else
- func (stream, "{d%d-d%d}", regno, regno + offset - 1);
+ {
+ func (stream, dis_style_register, "d%d", regno);
+ func (stream, dis_style_text, "-");
+ func (stream, dis_style_register, "d%d",
+ regno + offset - 1);
+ }
+ func (stream, dis_style_text, "}");
}
break;
case 'C':
{
- bfd_boolean single = ((given >> 8) & 1) == 0;
+ bool single = ((given >> 8) & 1) == 0;
char reg_prefix = single ? 's' : 'd';
int Dreg = (given >> 22) & 0x1;
int Vdreg = (given >> 12) & 0xf;
int maxreg = single ? 31 : 15;
int topreg = reg + num - 1;
+ func (stream, dis_style_text, "{");
if (!num)
- func (stream, "{VPR}");
+ {
+ /* Nothing. */
+ }
else if (num == 1)
- func (stream, "{%c%d, VPR}", reg_prefix, reg);
+ {
+ func (stream, dis_style_register,
+ "%c%d", reg_prefix, reg);
+ func (stream, dis_style_text, ", ");
+ }
else if (topreg > maxreg)
- func (stream, "{%c%d-<overflow reg d%d, VPR}",
- reg_prefix, reg, single ? topreg >> 1 : topreg);
+ {
+ func (stream, dis_style_register, "%c%d",
+ reg_prefix, reg);
+ func (stream, dis_style_text, "-<overflow reg d%d, ",
+ single ? topreg >> 1 : topreg);
+ }
else
- func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
- reg_prefix, topreg);
+ {
+ func (stream, dis_style_register,
+ "%c%d", reg_prefix, reg);
+ func (stream, dis_style_text, "-");
+ func (stream, dis_style_register, "%c%d",
+ reg_prefix, topreg);
+ func (stream, dis_style_text, ", ");
+ }
+ func (stream, dis_style_register, "VPR");
+ func (stream, dis_style_text, "}");
}
break;
case 'u':
if (cond != COND_UNCOND)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'c':
if (cond != COND_UNCOND && cp_num == 9)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
- func (stream, "%s", arm_conditional[cond]);
+ /* Fall through. */
+ case 'b':
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional[cond]);
break;
case 'I':
if (imm & 0x40)
imm -= 0x80;
- func (stream, "%d", imm);
+ func (stream, dis_style_immediate, "%d", imm);
}
break;
switch (regno)
{
case 0x1:
- func (stream, "FPSCR");
+ func (stream, dis_style_register, "FPSCR");
break;
case 0x2:
- func (stream, "FPSCR_nzcvqc");
+ func (stream, dis_style_register, "FPSCR_nzcvqc");
break;
case 0xc:
- func (stream, "VPR");
+ func (stream, dis_style_register, "VPR");
break;
case 0xd:
- func (stream, "P0");
+ func (stream, dis_style_register, "P0");
break;
case 0xe:
- func (stream, "FPCXTNS");
+ func (stream, dis_style_register, "FPCXTNS");
break;
case 0xf:
- func (stream, "FPCXTS");
+ func (stream, dis_style_register, "FPCXTS");
break;
default:
- func (stream, "<invalid reg %lu>", regno);
+ func (stream, dis_style_text, "<invalid reg %lu>",
+ regno);
break;
}
}
switch (given & 0x00408000)
{
case 0:
- func (stream, "4");
+ func (stream, dis_style_immediate, "4");
break;
case 0x8000:
- func (stream, "1");
+ func (stream, dis_style_immediate, "1");
break;
case 0x00400000:
- func (stream, "2");
+ func (stream, dis_style_immediate, "2");
break;
default:
- func (stream, "3");
+ func (stream, dis_style_immediate, "3");
}
break;
switch (given & 0x00080080)
{
case 0:
- func (stream, "s");
+ func (stream, dis_style_mnemonic, "s");
break;
case 0x80:
- func (stream, "d");
+ func (stream, dis_style_mnemonic, "d");
break;
case 0x00080000:
- func (stream, "e");
+ func (stream, dis_style_mnemonic, "e");
break;
default:
- func (stream, _("<illegal precision>"));
+ func (stream, dis_style_text, _("<illegal precision>"));
break;
}
break;
switch (given & 0x00408000)
{
case 0:
- func (stream, "s");
+ func (stream, dis_style_mnemonic, "s");
break;
case 0x8000:
- func (stream, "d");
+ func (stream, dis_style_mnemonic, "d");
break;
case 0x00400000:
- func (stream, "e");
+ func (stream, dis_style_mnemonic, "e");
break;
default:
- func (stream, "p");
+ func (stream, dis_style_mnemonic, "p");
break;
}
break;
case 0:
break;
case 0x20:
- func (stream, "p");
+ func (stream, dis_style_mnemonic, "p");
break;
case 0x40:
- func (stream, "m");
+ func (stream, dis_style_mnemonic, "m");
break;
default:
- func (stream, "z");
+ func (stream, dis_style_mnemonic, "z");
break;
}
break;
{
case 'R':
if (value == 15)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'r':
if (c[1] == 'u')
++ c;
if (u_reg == value)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
u_reg = value;
}
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
break;
case 'V':
if (given & (1 << 6))
goto Q;
/* FALLTHROUGH */
case 'D':
- func (stream, "d%ld", value);
+ func (stream, dis_style_register, "d%ld", value);
break;
case 'Q':
Q:
if (value & 1)
- func (stream, "<illegal reg q%ld.5>", value >> 1);
+ func (stream, dis_style_text,
+ "<illegal reg q%ld.5>", value >> 1);
else
- func (stream, "q%ld", value >> 1);
+ func (stream, dis_style_register,
+ "q%ld", value >> 1);
break;
case 'd':
- func (stream, "%ld", value);
+ func (stream, base_style, "%ld", value);
value_in_comment = value;
break;
case 'E':
(16 + (value & 0xF));
if (!(decVal % 1000000))
- func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
- floatVal, value & 0x80 ? '-' : ' ',
- decVal / 10000000,
- decVal % 10000000 / 1000000);
+ {
+ func (stream, dis_style_immediate, "%ld", value);
+ func (stream, dis_style_comment_start,
+ "\t@ 0x%08x %c%u.%01u",
+ floatVal, value & 0x80 ? '-' : ' ',
+ decVal / 10000000,
+ decVal % 10000000 / 1000000);
+ }
else if (!(decVal % 10000))
- func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
- floatVal, value & 0x80 ? '-' : ' ',
- decVal / 10000000,
- decVal % 10000000 / 10000);
+ {
+ func (stream, dis_style_immediate, "%ld", value);
+ func (stream, dis_style_comment_start,
+ "\t@ 0x%08x %c%u.%03u",
+ floatVal, value & 0x80 ? '-' : ' ',
+ decVal / 10000000,
+ decVal % 10000000 / 10000);
+ }
else
- func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
- floatVal, value & 0x80 ? '-' : ' ',
- decVal / 10000000, decVal % 10000000);
+ {
+ func (stream, dis_style_immediate, "%ld", value);
+ func (stream, dis_style_comment_start,
+ "\t@ 0x%08x %c%u.%07u",
+ floatVal, value & 0x80 ? '-' : ' ',
+ decVal / 10000000, decVal % 10000000);
+ }
break;
}
case 'k':
{
int from = (given & (1 << 7)) ? 32 : 16;
- func (stream, "%ld", from - value);
+ func (stream, dis_style_immediate, "%ld",
+ from - value);
}
break;
case 'f':
if (value > 7)
- func (stream, "#%s", arm_fp_const[value & 7]);
+ func (stream, dis_style_immediate, "#%s",
+ arm_fp_const[value & 7]);
else
- func (stream, "f%ld", value);
+ func (stream, dis_style_register, "f%ld", value);
break;
case 'w':
if (width == 2)
- func (stream, "%s", iwmmxt_wwnames[value]);
+ func (stream, dis_style_mnemonic, "%s",
+ iwmmxt_wwnames[value]);
else
- func (stream, "%s", iwmmxt_wwssnames[value]);
+ func (stream, dis_style_mnemonic, "%s",
+ iwmmxt_wwssnames[value]);
break;
case 'g':
- func (stream, "%s", iwmmxt_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ iwmmxt_regnames[value]);
break;
case 'G':
- func (stream, "%s", iwmmxt_cregnames[value]);
+ func (stream, dis_style_register, "%s",
+ iwmmxt_cregnames[value]);
break;
case 'x':
- func (stream, "0x%lx", (value & 0xffffffffUL));
+ func (stream, dis_style_immediate, "0x%lx",
+ (value & 0xffffffffUL));
break;
case 'c':
switch (value)
{
case 0:
- func (stream, "eq");
+ func (stream, dis_style_mnemonic, "eq");
break;
case 1:
- func (stream, "vs");
+ func (stream, dis_style_mnemonic, "vs");
break;
case 2:
- func (stream, "ge");
+ func (stream, dis_style_mnemonic, "ge");
break;
case 3:
- func (stream, "gt");
+ func (stream, dis_style_mnemonic, "gt");
break;
default:
- func (stream, "??");
+ func (stream, dis_style_text, "??");
break;
}
break;
case '`':
c++;
if (value == 0)
- func (stream, "%c", *c);
+ func (stream, dis_style_mnemonic, "%c", *c);
break;
case '\'':
c++;
if (value == ((1ul << width) - 1))
- func (stream, "%c", *c);
+ func (stream, base_style, "%c", *c);
break;
case '?':
- func (stream, "%c", c[(1 << width) - (int) value]);
+ func (stream, base_style, "%c",
+ c[(1 << width) - (int) value]);
c += 1 << width;
break;
default:
break;
case '3': /* List */
- func (stream, "{");
+ func (stream, dis_style_text, "{");
regno = (given >> 12) & 0x0000000f;
if (single)
{
abort ();
}
- func (stream, "%c%d", single ? 's' : 'd', regno);
+ func (stream, dis_style_register, "%c%d",
+ single ? 's' : 'd', regno);
if (*c == '3')
{
if (--count)
{
- func (stream, "-%c%d",
+ func (stream, dis_style_text, "-");
+ func (stream, dis_style_register, "%c%d",
single ? 's' : 'd',
regno + count);
}
- func (stream, "}");
+ func (stream, dis_style_text, "}");
}
else if (*c == '4')
- func (stream, ", %c%d", single ? 's' : 'd',
- regno + 1);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%c%d",
+ single ? 's' : 'd', regno + 1);
+ }
}
break;
case 'L':
switch (given & 0x00400100)
{
- case 0x00000000: func (stream, "b"); break;
- case 0x00400000: func (stream, "h"); break;
- case 0x00000100: func (stream, "w"); break;
- case 0x00400100: func (stream, "d"); break;
+ case 0x00000000:
+ func (stream, dis_style_mnemonic, "b");
+ break;
+ case 0x00400000:
+ func (stream, dis_style_mnemonic, "h");
+ break;
+ case 0x00000100:
+ func (stream, dis_style_mnemonic, "w");
+ break;
+ case 0x00400100:
+ func (stream, dis_style_mnemonic, "d");
+ break;
default:
break;
}
{
/* given (20, 23) | given (0, 3) */
value = ((given >> 16) & 0xf0) | (given & 0xf);
- func (stream, "%d", (int) value);
+ func (stream, dis_style_immediate, "%d", (int) value);
}
break;
int offset = given & 0xff;
int multiplier = (given & 0x00000100) ? 4 : 1;
- func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s",
+ arm_regnames [(given >> 16) & 0xf]);
if (multiplier > 1)
{
if (offset)
{
if (PRE_BIT_SET)
- func (stream, ", #%s%d]%s",
- NEGATIVE_BIT_SET ? "-" : "",
- offset * multiplier,
- WRITEBACK_BIT_SET ? "!" : "");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%s%d",
+ NEGATIVE_BIT_SET ? "-" : "",
+ offset * multiplier);
+ func (stream, dis_style_text, "]%s",
+ WRITEBACK_BIT_SET ? "!" : "");
+ }
else
- func (stream, "], #%s%d",
- NEGATIVE_BIT_SET ? "-" : "",
- offset * multiplier);
+ {
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%s%d",
+ NEGATIVE_BIT_SET ? "-" : "",
+ offset * multiplier);
+ }
}
else
- func (stream, "]");
+ func (stream, dis_style_text, "]");
}
break;
{
case 1:
case 3:
- func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s", rn);
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_text, "%c", ubit ? '+' : '-');
+ func (stream, dis_style_register, "%s", rm);
if (imm4)
- func (stream, ", lsl #%d", imm4);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "lsl ");
+ func (stream, dis_style_immediate, "#%d", imm4);
+ }
break;
case 4:
case 5:
case 6:
case 7:
- func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s", rn);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_text, "%c", ubit ? '+' : '-');
+ func (stream, dis_style_register, "%s", rm);
if (imm4 > 0)
- func (stream, ", lsl #%d", imm4);
- func (stream, "]");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "lsl ");
+ func (stream, dis_style_immediate, "#%d", imm4);
+ }
+ func (stream, dis_style_text, "]");
if (puw_bits == 5 || puw_bits == 7)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
break;
default:
- func (stream, "INVALID");
+ func (stream, dis_style_text, "INVALID");
}
}
break;
{
long imm5;
imm5 = ((given & 0x100) >> 4) | (given & 0xf);
- func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
+ func (stream, dis_style_immediate, "%ld",
+ (imm5 == 0) ? 32 : imm5);
}
break;
}
}
else
- func (stream, "%c", *c);
+ {
+ if (*c == '@')
+ base_style = dis_style_comment_start;
+
+ if (*c == '\t')
+ base_style = dis_style_text;
+
+ func (stream, base_style, "%c", *c);
+ }
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
+ func (stream, dis_style_comment_start, "\t@ 0x%lx",
+ (value_in_comment & 0xffffffffUL));
if (is_unpredictable)
- func (stream, UNPREDICTABLE_INSTRUCTION);
+ func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
+}
+
+static bool
+print_insn_coprocessor (bfd_vma pc,
+ struct disassemble_info *info,
+ long given,
+ bool thumb)
+{
+ return print_insn_coprocessor_1 (coprocessor_opcodes,
+ pc, info, given, thumb);
+}
+
+static bool
+print_insn_generic_coprocessor (bfd_vma pc,
+ struct disassemble_info *info,
+ long given,
+ bool thumb)
+{
+ return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
+ pc, info, given, thumb);
}
/* Decodes and prints ARM addressing modes. Returns the offset
print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
{
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
bfd_vma offset = 0;
if (((given & 0x000f0000) == 0x000f0000)
{
offset = given & 0xfff;
- func (stream, "[pc");
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "pc");
if (PRE_BIT_SET)
{
/* Pre-indexed. Elide offset of positive zero when
non-writeback. */
if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
- func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%s%d",
+ NEGATIVE_BIT_SET ? "-" : "", (int) offset);
+ }
if (NEGATIVE_BIT_SET)
offset = -offset;
being used. Probably a very dangerous thing
for the programmer to do, but who are we to
argue ? */
- func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
+ func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : "");
}
else /* Post indexed. */
{
- func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%s%d",
+ NEGATIVE_BIT_SET ? "-" : "", (int) offset);
/* Ie ignore the offset. */
offset = pc + 8;
}
- func (stream, "\t; ");
+ func (stream, dis_style_comment_start, "\t@ ");
info->print_address_func (offset, info);
offset = 0;
}
else
{
- func (stream, "[%s",
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s",
arm_regnames[(given >> 16) & 0xf]);
if (PRE_BIT_SET)
/* Elide offset of positive zero when non-writeback. */
offset = given & 0xfff;
if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
- func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%s%d",
+ NEGATIVE_BIT_SET ? "-" : "", (int) offset);
+ }
}
else
{
- func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
- arm_decode_shift (given, func, stream, TRUE);
+ func (stream, dis_style_text, ", %s",
+ NEGATIVE_BIT_SET ? "-" : "");
+ arm_decode_shift (given, func, stream, true);
}
- func (stream, "]%s",
+ func (stream, dis_style_text, "]%s",
WRITEBACK_BIT_SET ? "!" : "");
}
else
{
/* Always show offset. */
offset = given & 0xfff;
- func (stream, "], #%s%d",
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%s%d",
NEGATIVE_BIT_SET ? "-" : "", (int) offset);
}
else
{
- func (stream, "], %s",
+ func (stream, dis_style_text, "], %s",
NEGATIVE_BIT_SET ? "-" : "");
- arm_decode_shift (given, func, stream, TRUE);
+ arm_decode_shift (given, func, stream, true);
}
}
if (NEGATIVE_BIT_SET)
return (signed long) offset;
}
+
+/* Print one cde instruction on INFO->STREAM.
+ Return TRUE if the instuction matched, FALSE if this is not a
+ recognised cde instruction. */
+static bool
+print_insn_cde (struct disassemble_info *info, long given, bool thumb)
+{
+ const struct cdeopcode32 *insn;
+ void *stream = info->stream;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
+
+ if (thumb)
+ {
+ /* Manually extract the coprocessor code from a known point.
+ This position is the same across all CDE instructions. */
+ for (insn = cde_opcodes; insn->assembler; insn++)
+ {
+ uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
+ uint16_t coproc_mask = 1 << coproc;
+ if (! (coproc_mask & cde_coprocs))
+ continue;
+
+ if ((given & insn->mask) == insn->value)
+ {
+ bool is_unpredictable = false;
+ const char *c;
+
+ for (c = insn->assembler; *c; c++)
+ {
+ if (*c == '%')
+ {
+ switch (*++c)
+ {
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
+ case '%':
+ func (stream, base_style, "%%");
+ break;
+
+ case '0': case '1': case '2': case '3': case '4':
+ case '5': case '6': case '7': case '8': case '9':
+ {
+ int width;
+ unsigned long value;
+
+ c = arm_decode_bitfield (c, given, &value, &width);
+
+ switch (*c)
+ {
+ case 'S':
+ if (value > 10)
+ is_unpredictable = true;
+ /* Fall through. */
+ case 'R':
+ if (value == 13)
+ is_unpredictable = true;
+ /* Fall through. */
+ case 'r':
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
+ break;
+
+ case 'n':
+ if (value == 15)
+ func (stream, dis_style_register, "%s", "APSR_nzcv");
+ else
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
+ break;
+
+ case 'T':
+ func (stream, dis_style_register, "%s",
+ arm_regnames[(value + 1) & 15]);
+ break;
+
+ case 'd':
+ func (stream, dis_style_immediate, "%ld", value);
+ break;
+
+ case 'V':
+ if (given & (1 << 6))
+ func (stream, dis_style_register, "q%ld", value >> 1);
+ else if (given & (1 << 24))
+ func (stream, dis_style_register, "d%ld", value);
+ else
+ {
+ /* Encoding for S register is different than for D and
+ Q registers. S registers are encoded using the top
+ single bit in position 22 as the lowest bit of the
+ register number, while for Q and D it represents the
+ highest bit of the register number. */
+ uint8_t top_bit = (value >> 4) & 1;
+ uint8_t tmp = (value << 1) & 0x1e;
+ uint8_t res = tmp | top_bit;
+ func (stream, dis_style_register, "s%u", res);
+ }
+ break;
+
+ default:
+ abort ();
+ }
+ }
+ break;
+
+ case 'p':
+ {
+ uint8_t proc_number = (given >> 8) & 0x7;
+ func (stream, dis_style_register, "p%u", proc_number);
+ break;
+ }
+
+ case 'a':
+ {
+ uint8_t a_offset = 28;
+ if (given & (1 << a_offset))
+ func (stream, dis_style_mnemonic, "a");
+ break;
+ }
+ default:
+ abort ();
+ }
+ }
+ else
+ {
+ if (*c == '@')
+ base_style = dis_style_comment_start;
+ if (*c == '\t')
+ base_style = dis_style_text;
+
+ func (stream, base_style, "%c", *c);
+ }
+ }
+
+ if (is_unpredictable)
+ func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
+
+ return true;
+ }
+ }
+ return false;
+ }
+ else
+ return false;
+}
+
+
/* Print one neon instruction on INFO->STREAM.
Return TRUE if the instuction matched, FALSE if this is not a
recognised neon instruction. */
-static bfd_boolean
-print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+static bool
+print_insn_neon (struct disassemble_info *info, long given, bool thumb)
{
const struct opcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
if (thumb)
{
}
else if ((given & 0xff000000) == 0xf9000000)
given ^= 0xf9000000 ^ 0xf4000000;
+ /* BFloat16 neon instructions without special top byte handling. */
+ else if ((given & 0xff000000) == 0xfe000000
+ || (given & 0xff000000) == 0xfc000000)
+ ;
/* vdup is also a valid neon instruction. */
- else if ((given & 0xff910f5f) != 0xee800b10)
- return FALSE;
+ else if ((given & 0xff900f5f) != 0xee800b10)
+ return false;
}
for (insn = neon_opcodes; insn->assembler; insn++)
{
- if ((given & insn->mask) == insn->value)
+ unsigned long cond_mask = insn->mask;
+ unsigned long cond_value = insn->value;
+ int cond;
+
+ if (thumb)
+ {
+ if ((cond_mask & 0xf0000000) == 0) {
+ /* For the entries in neon_opcodes, an opcode mask/value with
+ the high 4 bits equal to 0 indicates a conditional
+ instruction. For thumb however, we need to include those
+ bits in the instruction matching. */
+ cond_mask |= 0xf0000000;
+ /* Furthermore, the thumb encoding of a conditional instruction
+ will have the high 4 bits equal to 0xe. */
+ cond_value |= 0xe0000000;
+ }
+ if (ifthen_state)
+ cond = IFTHEN_COND;
+ else
+ cond = COND_UNCOND;
+ }
+ else
+ {
+ if ((given & 0xf0000000) == 0xf0000000)
+ {
+ /* If the instruction is unconditional, update the mask to only
+ match against unconditional opcode values. */
+ cond_mask |= 0xf0000000;
+ cond = COND_UNCOND;
+ }
+ else
+ {
+ cond = (given >> 28) & 0xf;
+ if (cond == 0xe)
+ cond = COND_UNCOND;
+ }
+ }
+
+ if ((given & cond_mask) == cond_value)
{
signed long value_in_comment = 0;
- bfd_boolean is_unpredictable = FALSE;
+ bool is_unpredictable = false;
const char *c;
for (c = insn->assembler; *c; c++)
{
switch (*++c)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case 'u':
if (thumb && ifthen_state)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'c':
- if (thumb && ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional[cond]);
break;
case 'A':
int stride = (enc[type] >> 4) + 1;
int ix;
- func (stream, "{");
+ func (stream, dis_style_text, "{");
if (stride > 1)
for (ix = 0; ix != n; ix++)
- func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
+ {
+ if (ix > 0)
+ func (stream, dis_style_text, ",");
+ func (stream, dis_style_register, "d%d",
+ rd + ix * stride);
+ }
else if (n == 1)
- func (stream, "d%d", rd);
+ func (stream, dis_style_register, "d%d", rd);
else
- func (stream, "d%d-d%d", rd, rd + n - 1);
- func (stream, "}, [%s", arm_regnames[rn]);
+ {
+ func (stream, dis_style_register, "d%d", rd);
+ func (stream, dis_style_text, "-");
+ func (stream, dis_style_register, "d%d",
+ rd + n - 1);
+ }
+ func (stream, dis_style_text, "}, [");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[rn]);
if (align)
- func (stream, " :%d", 32 << align);
- func (stream, "]");
+ {
+ func (stream, dis_style_text, " :");
+ func (stream, dis_style_immediate, "%d",
+ 32 << align);
+ }
+ func (stream, dis_style_text, "]");
if (rm == 0xd)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
else if (rm != 0xf)
- func (stream, ", %s", arm_regnames[rm]);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[rm]);
+ }
}
break;
{
int amask = (1 << size) - 1;
if ((idx_align & (1 << size)) != 0)
- return FALSE;
+ return false;
if (size > 0)
{
if ((idx_align & amask) == amask)
align = 8 << size;
else if ((idx_align & amask) != 0)
- return FALSE;
+ return false;
}
}
break;
case 2:
if (size == 2 && (idx_align & 2) != 0)
- return FALSE;
+ return false;
align = (idx_align & 1) ? 16 << size : 0;
break;
case 3:
if ((size == 2 && (idx_align & 3) != 0)
|| (idx_align & 1) != 0)
- return FALSE;
+ return false;
break;
case 4:
if (size == 2)
{
if ((idx_align & 3) == 3)
- return FALSE;
+ return false;
align = (idx_align & 3) * 64;
}
else
abort ();
}
- func (stream, "{");
+ func (stream, dis_style_text, "{");
for (i = 0; i < length; i++)
- func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
- rd + i * stride, idx);
- func (stream, "}, [%s", arm_regnames[rn]);
+ {
+ if (i > 0)
+ func (stream, dis_style_text, ",");
+ func (stream, dis_style_register, "d%d[%d]",
+ rd + i * stride, idx);
+ }
+ func (stream, dis_style_text, "}, [");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[rn]);
if (align)
- func (stream, " :%d", align);
- func (stream, "]");
+ {
+ func (stream, dis_style_text, " :");
+ func (stream, dis_style_immediate, "%d", align);
+ }
+ func (stream, dis_style_text, "]");
if (rm == 0xd)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
else if (rm != 0xf)
- func (stream, ", %s", arm_regnames[rm]);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[rm]);
+ }
}
break;
else
stride++;
- func (stream, "{");
+ func (stream, dis_style_text, "{");
if (stride > 1)
for (ix = 0; ix != n; ix++)
- func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
+ {
+ if (ix > 0)
+ func (stream, dis_style_text, ",");
+ func (stream, dis_style_register, "d%d[]",
+ rd + ix * stride);
+ }
else if (n == 1)
- func (stream, "d%d[]", rd);
+ func (stream, dis_style_register, "d%d[]", rd);
else
- func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
- func (stream, "}, [%s", arm_regnames[rn]);
+ {
+ func (stream, dis_style_register, "d%d[]", rd);
+ func (stream, dis_style_text, "-");
+ func (stream, dis_style_register, "d%d[]",
+ rd + n - 1);
+ }
+ func (stream, dis_style_text, "}, [");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[rn]);
if (align)
{
align = (8 * (type + 1)) << size;
if (type == 3)
align = (size > 1) ? align >> 1 : align;
if (type == 2 || (type == 0 && !size))
- func (stream, " :<bad align %d>", align);
+ func (stream, dis_style_text,
+ " :<bad align %d>", align);
else
- func (stream, " :%d", align);
+ {
+ func (stream, dis_style_text, " :");
+ func (stream, dis_style_immediate,
+ "%d", align);
+ }
}
- func (stream, "]");
+ func (stream, dis_style_text, "]");
if (rm == 0xd)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
else if (rm != 0xf)
- func (stream, ", %s", arm_regnames[rm]);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[rm]);
+ }
}
break;
int reg = raw_reg & ((4 << size) - 1);
int ix = raw_reg >> size >> 2;
- func (stream, "d%d[%d]", reg, ix);
+ func (stream, dis_style_register, "d%d[%d]", reg, ix);
}
break;
}
else
{
- func (stream, "<illegal constant %.8x:%x:%x>",
+ func (stream, dis_style_text,
+ "<illegal constant %.8x:%x:%x>",
bits, cmode, op);
size = 32;
break;
switch (size)
{
case 8:
- func (stream, "#%ld\t; 0x%.2lx", value, value);
+ func (stream, dis_style_immediate, "#%ld", value);
+ func (stream, dis_style_comment_start,
+ "\t@ 0x%.2lx", value);
break;
case 16:
- func (stream, "#%ld\t; 0x%.4lx", value, value);
+ func (stream, dis_style_immediate, "#%ld", value);
+ func (stream, dis_style_comment_start,
+ "\t@ 0x%.4lx", value);
break;
case 32:
(& floatformat_ieee_single_little, valbytes,
& fvalue);
- func (stream, "#%.7g\t; 0x%.8lx", fvalue,
- value);
+ func (stream, dis_style_immediate,
+ "#%.7g", fvalue);
+ func (stream, dis_style_comment_start,
+ "\t@ 0x%.8lx", value);
}
else
- func (stream, "#%ld\t; 0x%.8lx",
- (long) (((value & 0x80000000L) != 0)
- ? value | ~0xffffffffL : value),
- value);
+ {
+ func (stream, dis_style_immediate, "#%ld",
+ (long) (((value & 0x80000000L) != 0)
+ ? value | ~0xffffffffL : value));
+ func (stream, dis_style_comment_start,
+ "\t@ 0x%.8lx", value);
+ }
break;
case 64:
- func (stream, "#0x%.8lx%.8lx", hival, value);
+ func (stream, dis_style_immediate,
+ "#0x%.8lx%.8lx", hival, value);
break;
default:
int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
int num = (given >> 8) & 0x3;
+ func (stream, dis_style_text, "{");
if (!num)
- func (stream, "{d%d}", regno);
+ func (stream, dis_style_register, "d%d", regno);
else if (num + regno >= 32)
- func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
+ {
+ func (stream, dis_style_register, "d%d", regno);
+ func (stream, dis_style_text, "-<overflow reg d%d",
+ regno + num);
+ }
else
- func (stream, "{d%d-d%d}", regno, regno + num);
+ {
+ func (stream, dis_style_register, "d%d", regno);
+ func (stream, dis_style_text, "-");
+ func (stream, dis_style_register, "d%d",
+ regno + num);
+ }
+ func (stream, dis_style_text, "}");
}
break;
switch (*c)
{
case 'r':
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
break;
case 'd':
- func (stream, "%ld", value);
+ func (stream, base_style, "%ld", value);
value_in_comment = value;
break;
case 'e':
- func (stream, "%ld", (1ul << width) - value);
+ func (stream, dis_style_immediate, "%ld",
+ (1ul << width) - value);
break;
case 'S':
high = limit & 3;
if (value < low || value > high)
- func (stream, "<illegal width %d>", base << value);
+ func (stream, dis_style_text,
+ "<illegal width %d>", base << value);
else
- func (stream, "%d", base << value);
+ func (stream, base_style, "%d",
+ base << value);
}
break;
case 'R':
goto Q;
/* FALLTHROUGH */
case 'D':
- func (stream, "d%ld", value);
+ func (stream, dis_style_register, "d%ld", value);
break;
case 'Q':
Q:
if (value & 1)
- func (stream, "<illegal reg q%ld.5>", value >> 1);
+ func (stream, dis_style_text,
+ "<illegal reg q%ld.5>", value >> 1);
else
- func (stream, "q%ld", value >> 1);
+ func (stream, dis_style_register,
+ "q%ld", value >> 1);
break;
case '`':
c++;
if (value == 0)
- func (stream, "%c", *c);
+ func (stream, dis_style_text, "%c", *c);
break;
case '\'':
c++;
if (value == ((1ul << width) - 1))
- func (stream, "%c", *c);
+ func (stream, dis_style_text, "%c", *c);
break;
case '?':
- func (stream, "%c", c[(1 << width) - (int) value]);
+ func (stream, dis_style_mnemonic, "%c",
+ c[(1 << width) - (int) value]);
c += 1 << width;
break;
default:
}
}
else
- func (stream, "%c", *c);
+ {
+ if (*c == '@')
+ base_style = dis_style_comment_start;
+
+ if (*c == '\t')
+ base_style = dis_style_text;
+
+ func (stream, base_style, "%c", *c);
+
+ }
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, dis_style_comment_start, "\t@ 0x%lx",
+ value_in_comment);
if (is_unpredictable)
- func (stream, UNPREDICTABLE_INSTRUCTION);
+ func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
/* Print one mve instruction on INFO->STREAM.
Return TRUE if the instuction matched, FALSE if this is not a
recognised mve instruction. */
-static bfd_boolean
+static bool
print_insn_mve (struct disassemble_info *info, long given)
{
const struct mopcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
for (insn = mve_opcodes; insn->assembler; insn++)
{
&& !is_mve_encoding_conflict (given, insn->mve_op))
{
signed long value_in_comment = 0;
- bfd_boolean is_unpredictable = FALSE;
- bfd_boolean is_undefined = FALSE;
+ bool is_unpredictable = false;
+ bool is_undefined = false;
const char *c;
enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
enum mve_undefined undefined_cond = UNDEF_NONE;
There are a few exceptions; check for them. */
if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
{
- is_unpredictable = TRUE;
+ is_unpredictable = true;
unpredictable_cond = UNPRED_IT_BLOCK;
}
else if (is_mve_unpredictable (given, insn->mve_op,
&unpredictable_cond))
- is_unpredictable = TRUE;
+ is_unpredictable = true;
if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
- is_undefined = TRUE;
+ is_undefined = true;
+
+ /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
+ i.e "VMOV Qd, Qm". */
+ if ((insn->mve_op == MVE_VORR_REG)
+ && (arm_decode_field (given, 1, 3)
+ == arm_decode_field (given, 17, 19)))
+ continue;
for (c = insn->assembler; *c; c++)
{
{
switch (*++c)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case 'a':
/* Don't print anything for '+' as it is implied. */
if (arm_decode_field (given, 23, 23) == 0)
- func (stream, "-");
+ func (stream, dis_style_immediate, "-");
break;
case 'c':
if (ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional[IFTHEN_COND]);
break;
case 'd':
case 'i':
{
long mve_mask = mve_extract_pred_mask (given);
- func (stream, "%s", mve_predicatenames[mve_mask]);
+ func (stream, dis_style_mnemonic, "%s",
+ mve_predicatenames[mve_mask]);
}
break;
+ case 'j':
+ {
+ unsigned int imm5 = 0;
+ imm5 |= arm_decode_field (given, 6, 7);
+ imm5 |= (arm_decode_field (given, 12, 14) << 2);
+ func (stream, dis_style_immediate, "#%u",
+ (imm5 == 0) ? 32 : imm5);
+ }
+ break;
+
+ case 'k':
+ func (stream, dis_style_immediate, "#%u",
+ (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
+ break;
+
case 'n':
print_vec_condition (info, given, insn->mve_op);
break;
= arm_decode_field (given, 4, 4)
| (arm_decode_field (given, 6, 6) << 1);
- func (stream, ", uxtw #%lu", size);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "uxtw ");
+ func (stream, dis_style_immediate, "#%lu", size);
}
break;
&& ((op1 == 0) || (op1 == 1)))
;
else
- func (stream, "s");
+ func (stream, dis_style_mnemonic, "s");
}
else
- func (stream, "u");
+ func (stream, dis_style_mnemonic, "u");
}
else
{
if (arm_decode_field (given, 28, 28) == 0)
- func (stream, "s");
+ func (stream, dis_style_mnemonic, "s");
else
- func (stream, "u");
+ func (stream, dis_style_mnemonic, "u");
}
}
break;
case 'w':
if (arm_decode_field (given, 21, 21) == 1)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
break;
case 'B':
case 'T':
if (arm_decode_field (given, 12, 12) == 0)
- func (stream, "b");
+ func (stream, dis_style_mnemonic, "b");
else
- func (stream, "t");
+ func (stream, dis_style_mnemonic, "t");
break;
case 'X':
if (arm_decode_field (given, 12, 12) == 1)
- func (stream, "x");
+ func (stream, dis_style_mnemonic, "x");
break;
case '0': case '1': case '2': case '3': case '4':
{
case 'Z':
if (value == 13)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
else if (value == 15)
- func (stream, "zr");
+ func (stream, dis_style_register, "zr");
+ else
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
+ break;
+
+ case 'c':
+ func (stream, dis_style_sub_mnemonic, "%s",
+ arm_conditional[value]);
+ break;
+
+ case 'C':
+ value ^= 1;
+ func (stream, dis_style_sub_mnemonic, "%s",
+ arm_conditional[value]);
+ break;
+
+ case 'S':
+ if (value == 13 || value == 15)
+ is_unpredictable = true;
else
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
break;
+
case 's':
print_mve_size (info,
value,
break;
case 'I':
if (value == 1)
- func (stream, "i");
+ func (stream, dis_style_mnemonic, "i");
break;
case 'A':
if (value == 1)
- func (stream, "a");
+ func (stream, dis_style_mnemonic, "a");
break;
case 'h':
{
unsigned int odd_reg = (value << 1) | 1;
- func (stream, "%s", arm_regnames[odd_reg]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[odd_reg]);
}
break;
case 'i':
break;
}
- func (stream, "%lu", mod_imm);
+ func (stream, dis_style_immediate, "%lu",
+ mod_imm);
}
break;
case 'k':
- func (stream, "%lu", 64 - value);
+ func (stream, dis_style_immediate, "%lu",
+ 64 - value);
break;
case 'l':
{
unsigned int even_reg = value << 1;
- func (stream, "%s", arm_regnames[even_reg]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[even_reg]);
}
break;
case 'u':
switch (value)
{
case 0:
- func (stream, "1");
+ func (stream, dis_style_immediate, "1");
break;
case 1:
- func (stream, "2");
+ func (stream, dis_style_immediate, "2");
break;
case 2:
- func (stream, "4");
+ func (stream, dis_style_immediate, "4");
break;
case 3:
- func (stream, "8");
+ func (stream, dis_style_immediate, "8");
break;
default:
break;
print_mve_rotate (info, value, width);
break;
case 'r':
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
break;
case 'd':
if (insn->mve_op == MVE_VQSHL_T2
switch (value)
{
case 0x00:
- func (stream, "8");
+ func (stream, dis_style_immediate, "8");
break;
case 0x01:
- func (stream, "16");
+ func (stream, dis_style_immediate, "16");
break;
case 0x10:
print_mve_undefined (info, UNDEF_SIZE_0);
{
if (insn->mve_op == MVE_VSHLC && value == 0)
value = 32;
- func (stream, "%ld", value);
+ func (stream, base_style, "%ld", value);
value_in_comment = value;
}
break;
case 'F':
- func (stream, "s%ld", value);
+ func (stream, dis_style_register, "s%ld", value);
break;
case 'Q':
if (value & 0x8)
- func (stream, "<illegal reg q%ld.5>", value);
+ func (stream, dis_style_text,
+ "<illegal reg q%ld.5>", value);
else
- func (stream, "q%ld", value);
+ func (stream, dis_style_register, "q%ld", value);
break;
case 'x':
- func (stream, "0x%08lx", value);
+ func (stream, dis_style_immediate,
+ "0x%08lx", value);
break;
default:
abort ();
}
}
else
- func (stream, "%c", *c);
+ {
+ if (*c == '@')
+ base_style = dis_style_comment_start;
+
+ if (*c == '\t')
+ base_style = dis_style_text;
+
+ func (stream, base_style, "%c", *c);
+ }
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, dis_style_comment_start, "\t@ 0x%lx",
+ value_in_comment);
if (is_unpredictable)
print_mve_unpredictable (info, unpredictable_cond);
if (is_undefined)
print_mve_undefined (info, undefined_cond);
- if ((vpt_block_state.in_vpt_block == FALSE)
+ if (!vpt_block_state.in_vpt_block
&& !ifthen_state
- && (is_vpt_instruction (given) == TRUE))
+ && is_vpt_instruction (given))
mark_inside_vpt_block (given);
- else if (vpt_block_state.in_vpt_block == TRUE)
+ else if (vpt_block_state.in_vpt_block)
update_vpt_block_state ();
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
{
const struct opcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
struct arm_private_data *private_data = info->private_data;
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
- if (print_insn_coprocessor (pc, info, given, FALSE))
+ if (print_insn_coprocessor (pc, info, given, false))
return;
- if (print_insn_neon (info, given, FALSE))
+ if (print_insn_neon (info, given, false))
+ return;
+
+ if (print_insn_generic_coprocessor (pc, info, given, false))
return;
for (insn = arm_opcodes; insn->assembler; insn++)
{
unsigned long u_reg = 16;
unsigned long U_reg = 16;
- bfd_boolean is_unpredictable = FALSE;
+ bool is_unpredictable = false;
signed long value_in_comment = 0;
const char *c;
{
if (*c == '%')
{
- bfd_boolean allow_unpredictable = FALSE;
+ bool allow_unpredictable = false;
switch (*++c)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case 'a':
break;
case 'S':
- allow_unpredictable = TRUE;
+ allow_unpredictable = true;
/* Fall through. */
case 's':
if ((given & 0x004f0000) == 0x004f0000)
{
/* Elide positive zero offset. */
if (offset || NEGATIVE_BIT_SET)
- func (stream, "[pc, #%s%d]\t; ",
- NEGATIVE_BIT_SET ? "-" : "", (int) offset);
+ {
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "pc");
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%s%d",
+ (NEGATIVE_BIT_SET ? "-" : ""),
+ (int) offset);
+ func (stream, dis_style_text, "]");
+ }
else
- func (stream, "[pc]\t; ");
+ {
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "pc");
+ func (stream, dis_style_text, "]");
+ }
if (NEGATIVE_BIT_SET)
offset = -offset;
+ func (stream, dis_style_comment_start, "\t@ ");
info->print_address_func (offset + pc + 8, info);
}
else
{
/* Always show the offset. */
- func (stream, "[pc], #%s%d",
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "pc");
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%s%d",
NEGATIVE_BIT_SET ? "-" : "", (int) offset);
if (! allow_unpredictable)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
}
}
else
{
int offset = ((given & 0xf00) >> 4) | (given & 0xf);
- func (stream, "[%s",
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s",
arm_regnames[(given >> 16) & 0xf]);
if (PRE_BIT_SET)
positive zero. */
if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
|| offset)
- func (stream, ", #%s%d",
- NEGATIVE_BIT_SET ? "-" : "", offset);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate,
+ "#%s%d",
+ (NEGATIVE_BIT_SET ? "-" : ""),
+ offset);
+ }
if (NEGATIVE_BIT_SET)
offset = -offset;
else
{
/* Register Offset or Register Pre-Indexed. */
- func (stream, ", %s%s",
- NEGATIVE_BIT_SET ? "-" : "",
+ func (stream, dis_style_text, ", %s",
+ NEGATIVE_BIT_SET ? "-" : "");
+ func (stream, dis_style_register, "%s",
arm_regnames[given & 0xf]);
/* Writing back to the register that is the source/
if (! allow_unpredictable
&& WRITEBACK_BIT_SET
&& ((given & 0xf) == ((given >> 12) & 0xf)))
- is_unpredictable = TRUE;
+ is_unpredictable = true;
}
- func (stream, "]%s",
+ func (stream, dis_style_text, "]%s",
WRITEBACK_BIT_SET ? "!" : "");
}
else
{
/* Immediate Post-indexed. */
/* PR 10924: Offset must be printed, even if it is zero. */
- func (stream, "], #%s%d",
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%s%d",
NEGATIVE_BIT_SET ? "-" : "", offset);
if (NEGATIVE_BIT_SET)
offset = -offset;
else
{
/* Register Post-indexed. */
- func (stream, "], %s%s",
- NEGATIVE_BIT_SET ? "-" : "",
+ func (stream, dis_style_text, "], %s",
+ NEGATIVE_BIT_SET ? "-" : "");
+ func (stream, dis_style_register, "%s",
arm_regnames[given & 0xf]);
/* Writing back to the register that is the source/
destination of the load/store is unpredictable. */
if (! allow_unpredictable
&& (given & 0xf) == ((given >> 12) & 0xf))
- is_unpredictable = TRUE;
+ is_unpredictable = true;
}
if (! allow_unpredictable)
/* Specifying the PC register as the post-indexed
registers is also unpredictable. */
|| (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
- is_unpredictable = TRUE;
+ is_unpredictable = true;
}
}
}
case 'b':
{
bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
- info->print_address_func (disp * 4 + pc + 8, info);
+ bfd_vma target = disp * 4 + pc + 8;
+ info->print_address_func (target, info);
+
+ /* Fill in instruction information. */
+ info->insn_info_valid = 1;
+ info->insn_type = dis_branch;
+ info->target = target;
}
break;
case 'c':
if (((given >> 28) & 0xf) != 0xe)
- func (stream, "%s",
+ func (stream, dis_style_mnemonic, "%s",
arm_conditional [(given >> 28) & 0xf]);
break;
int started = 0;
int reg;
- func (stream, "{");
+ func (stream, dis_style_text, "{");
for (reg = 0; reg < 16; reg++)
if ((given & (1 << reg)) != 0)
{
if (started)
- func (stream, ", ");
+ func (stream, dis_style_text, ", ");
started = 1;
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[reg]);
}
- func (stream, "}");
+ func (stream, dis_style_text, "}");
if (! started)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
}
break;
case 'q':
- arm_decode_shift (given, func, stream, FALSE);
+ arm_decode_shift (given, func, stream, false);
break;
case 'o':
unsigned int immed = (given & 0xff);
unsigned int a, i;
- a = (((immed << (32 - rotate))
- | (immed >> rotate)) & 0xffffffff);
+ a = (immed << ((32 - rotate) & 31)
+ | immed >> rotate) & 0xffffffff;
/* If there is another encoding with smaller rotate,
the rotate should be specified directly. */
for (i = 0; i < 32; i += 2)
- if ((a << i | a >> (32 - i)) <= 0xff)
+ if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
break;
if (i != rotate)
- func (stream, "#%d, %d", immed, rotate);
+ {
+ func (stream, dis_style_immediate, "#%d", immed);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "%d", rotate);
+ }
else
- func (stream, "#%d", a);
+ func (stream, dis_style_immediate, "#%d", a);
value_in_comment = a;
}
else
- arm_decode_shift (given, func, stream, TRUE);
+ arm_decode_shift (given, func, stream, true);
break;
case 'p':
obsolete in V6 onwards. */
if (! ARM_CPU_HAS_FEATURE (private_data->features, \
arm_ext_v6))
- func (stream, "p");
+ func (stream, dis_style_mnemonic, "p");
else
- is_unpredictable = TRUE;
+ is_unpredictable = true;
}
break;
case 't':
if ((given & 0x01200000) == 0x00200000)
- func (stream, "t");
+ func (stream, dis_style_mnemonic, "t");
break;
case 'A':
if (NEGATIVE_BIT_SET)
value_in_comment = - value_in_comment;
- func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
+ func (stream, dis_style_text, "[%s",
+ arm_regnames [(given >> 16) & 0xf]);
if (PRE_BIT_SET)
{
if (offset)
- func (stream, ", #%d]%s",
+ func (stream, dis_style_text, ", #%d]%s",
(int) value_in_comment,
WRITEBACK_BIT_SET ? "!" : "");
else
- func (stream, "]");
+ func (stream, dis_style_text, "]");
}
else
{
- func (stream, "]");
+ func (stream, dis_style_text, "]");
if (WRITEBACK_BIT_SET)
{
if (offset)
- func (stream, ", #%d", (int) value_in_comment);
+ func (stream, dis_style_text,
+ ", #%d", (int) value_in_comment);
}
else
{
- func (stream, ", {%d}", (int) offset);
+ func (stream, dis_style_text,
+ ", {%d}", (int) offset);
value_in_comment = offset;
}
}
address += 2;
info->print_address_func (address, info);
+
+ /* Fill in instruction information. */
+ info->insn_info_valid = 1;
+ info->insn_type = dis_branch;
+ info->target = address;
}
break;
name = banked_regname (sysm);
if (name != NULL)
- func (stream, "%s", name);
+ func (stream, dis_style_register, "%s", name);
else
- func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
+ func (stream, dis_style_text,
+ "(UNDEF: %lu)", (unsigned long) sysm);
}
else
{
- func (stream, "%cPSR_",
+ func (stream, dis_style_register, "%cPSR_",
(given & 0x00400000) ? 'S' : 'C');
+
if (given & 0x80000)
- func (stream, "f");
+ func (stream, dis_style_register, "f");
if (given & 0x40000)
- func (stream, "s");
+ func (stream, dis_style_register, "s");
if (given & 0x20000)
- func (stream, "x");
+ func (stream, dis_style_register, "x");
if (given & 0x10000)
- func (stream, "c");
+ func (stream, dis_style_register, "c");
}
break;
{
switch (given & 0xf)
{
- case 0xf: func (stream, "sy"); break;
+ case 0xf:
+ func (stream, dis_style_sub_mnemonic, "sy");
+ break;
default:
- func (stream, "#%d", (int) given & 0xf);
+ func (stream, dis_style_immediate, "#%d",
+ (int) given & 0xf);
break;
}
}
{
const char * opt = data_barrier_option (given & 0xf);
if (opt != NULL)
- func (stream, "%s", opt);
+ func (stream, dis_style_sub_mnemonic, "%s", opt);
else
- func (stream, "#%d", (int) given & 0xf);
+ func (stream, dis_style_immediate,
+ "#%d", (int) given & 0xf);
}
break;
{
case 'R':
if (value == 15)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'r':
case 'T':
/* We want register + 1 when decoding T. */
if (*c == 'T')
- ++value;
+ value = (value + 1) & 0xf;
if (c[1] == 'u')
{
++ c;
if (u_reg == value)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
u_reg = value;
}
if (c[1] == 'U')
++ c;
if (U_reg == value)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
U_reg = value;
}
- func (stream, "%s", arm_regnames[value]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[value]);
break;
case 'd':
- func (stream, "%ld", value);
+ func (stream, base_style, "%ld", value);
value_in_comment = value;
break;
case 'b':
- func (stream, "%ld", value * 8);
+ func (stream, dis_style_immediate,
+ "%ld", value * 8);
value_in_comment = value * 8;
break;
case 'W':
- func (stream, "%ld", value + 1);
+ func (stream, dis_style_immediate,
+ "%ld", value + 1);
value_in_comment = value + 1;
break;
case 'x':
- func (stream, "0x%08lx", value);
+ func (stream, dis_style_immediate,
+ "0x%08lx", value);
/* Some SWI instructions have special
meanings. */
if ((given & 0x0fffffff) == 0x0FF00000)
- func (stream, "\t; IMB");
+ func (stream, dis_style_comment_start,
+ "\t@ IMB");
else if ((given & 0x0fffffff) == 0x0FF00001)
- func (stream, "\t; IMBRange");
+ func (stream, dis_style_comment_start,
+ "\t@ IMBRange");
break;
case 'X':
- func (stream, "%01lx", value & 0xf);
+ func (stream, dis_style_immediate,
+ "%01lx", value & 0xf);
value_in_comment = value;
break;
case '`':
c++;
if (value == 0)
- func (stream, "%c", *c);
+ func (stream, dis_style_text, "%c", *c);
break;
case '\'':
c++;
if (value == ((1ul << width) - 1))
- func (stream, "%c", *c);
+ func (stream, base_style, "%c", *c);
break;
case '?':
- func (stream, "%c", c[(1 << width) - (int) value]);
+ func (stream, base_style, "%c",
+ c[(1 << width) - (int) value]);
c += 1 << width;
break;
default:
int imm;
imm = (given & 0xf) | ((given & 0xfff00) >> 4);
- func (stream, "%d", imm);
+ func (stream, dis_style_immediate, "%d", imm);
value_in_comment = imm;
}
break;
long w = msb - lsb + 1;
if (w > 0)
- func (stream, "#%lu, #%lu", lsb, w);
+ {
+ func (stream, dis_style_immediate, "#%lu", lsb);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%lu", w);
+ }
else
- func (stream, "(invalid: %lu:%lu)", lsb, msb);
+ func (stream, dis_style_text,
+ "(invalid: %lu:%lu)", lsb, msb);
}
break;
name = banked_regname (sysm);
if (name != NULL)
- func (stream, "%s", name);
+ func (stream, dis_style_register, "%s", name);
else
- func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
+ func (stream, dis_style_text,
+ "(UNDEF: %lu)", (unsigned long) sysm);
}
break;
long lo = (given & 0x00000fff);
long imm16 = hi | lo;
- func (stream, "#%lu", imm16);
+ func (stream, dis_style_immediate, "#%lu", imm16);
value_in_comment = imm16;
}
break;
}
}
else
- func (stream, "%c", *c);
+ {
+
+ if (*c == '@')
+ base_style = dis_style_comment_start;
+
+ if (*c == '\t')
+ base_style = dis_style_text;
+
+ func (stream, base_style, "%c", *c);
+ }
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
+ func (stream, dis_style_comment_start, "\t@ 0x%lx",
+ (value_in_comment & 0xffffffffUL));
if (is_unpredictable)
- func (stream, UNPREDICTABLE_INSTRUCTION);
+ func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
return;
}
}
- func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
+ func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
+ (unsigned) given);
return;
}
{
const struct opcode16 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
for (insn = thumb_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
if (*c != '%')
{
- func (stream, "%c", *c);
+ if (*c == '@')
+ base_style = dis_style_comment_start;
+
+ if (*c == '\t')
+ base_style = dis_style_text;
+
+ func (stream, base_style, "%c", *c);
+
continue;
}
switch (*++c)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case 'c':
if (ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional[IFTHEN_COND]);
break;
case 'C':
if (ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional[IFTHEN_COND]);
else
- func (stream, "s");
+ func (stream, dis_style_mnemonic, "s");
break;
case 'I':
ifthen_next_state = given & 0xff;
for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
- func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
- func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
+ func (stream, dis_style_mnemonic,
+ ((given ^ tmp) & 0x10) ? "e" : "t");
+ func (stream, dis_style_text, "\t");
+ func (stream, dis_style_sub_mnemonic, "%s",
+ arm_conditional[(given >> 4) & 0xf]);
}
break;
case 'x':
if (ifthen_next_state)
- func (stream, "\t; unpredictable branch in IT block\n");
+ func (stream, dis_style_comment_start,
+ "\t@ unpredictable branch in IT block\n");
break;
case 'X':
if (ifthen_state)
- func (stream, "\t; unpredictable <IT:%s>",
+ func (stream, dis_style_comment_start,
+ "\t@ unpredictable <IT:%s>",
arm_conditional[IFTHEN_COND]);
break;
if (given & (1 << 6))
reg += 8;
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s", arm_regnames[reg]);
}
break;
if (given & (1 << 7))
reg += 8;
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s", arm_regnames[reg]);
}
break;
int started = 0;
int reg;
- func (stream, "{");
+ func (stream, dis_style_text, "{");
/* It would be nice if we could spot
ranges, and generate the rS-rE format: */
if ((given & (1 << reg)) != 0)
{
if (started)
- func (stream, ", ");
+ func (stream, dis_style_text, ", ");
started = 1;
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[reg]);
}
if (domasklr)
{
if (started)
- func (stream, ", ");
+ func (stream, dis_style_text, ", ");
started = 1;
- func (stream, "%s", arm_regnames[14] /* "lr" */);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[14] /* "lr" */);
}
if (domaskpc)
{
if (started)
- func (stream, ", ");
- func (stream, "%s", arm_regnames[15] /* "pc" */);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[15] /* "pc" */);
}
- func (stream, "}");
+ func (stream, dis_style_text, "}");
}
break;
writeback if the base register is not in the register
mask. */
if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
break;
case 'b':
+ ((given & 0x00f8) >> 2)
+ ((given & 0x0200) >> 3));
info->print_address_func (address, info);
+
+ /* Fill in instruction information. */
+ info->insn_info_valid = 1;
+ info->insn_type = dis_branch;
+ info->target = address;
}
break;
long imm = (given & 0x07c0) >> 6;
if (imm == 0)
imm = 32;
- func (stream, "#%ld", imm);
+ func (stream, dis_style_immediate, "#%ld", imm);
}
break;
if (!bitend)
abort ();
reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
+ reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1;
switch (*c)
{
case 'r':
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[reg]);
break;
case 'd':
- func (stream, "%ld", (long) reg);
+ func (stream, dis_style_immediate, "%ld",
+ (long) reg);
value_in_comment = reg;
break;
case 'H':
- func (stream, "%ld", (long) (reg << 1));
+ func (stream, dis_style_immediate, "%ld",
+ (long) (reg << 1));
value_in_comment = reg << 1;
break;
case 'W':
- func (stream, "%ld", (long) (reg << 2));
+ func (stream, dis_style_immediate, "%ld",
+ (long) (reg << 2));
value_in_comment = reg << 2;
break;
break;
case 'x':
- func (stream, "0x%04lx", (long) reg);
+ func (stream, dis_style_immediate, "0x%04lx",
+ (long) reg);
break;
case 'B':
reg = ((reg ^ (1 << bitend)) - (1 << bitend));
- info->print_address_func (reg * 2 + pc + 4, info);
+ bfd_vma target = reg * 2 + pc + 4;
+ info->print_address_func (target, info);
value_in_comment = 0;
+
+ /* Fill in instruction information. */
+ info->insn_info_valid = 1;
+ info->insn_type = dis_branch;
+ info->target = target;
break;
case 'c':
- func (stream, "%s", arm_conditional [reg]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional [reg]);
break;
default:
case '\'':
c++;
if ((given & (1 << bitstart)) != 0)
- func (stream, "%c", *c);
+ func (stream, base_style, "%c", *c);
break;
case '?':
++c;
if ((given & (1 << bitstart)) != 0)
- func (stream, "%c", *c++);
+ func (stream, base_style, "%c", *c++);
else
- func (stream, "%c", *++c);
+ func (stream, base_style, "%c", *++c);
break;
default:
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, dis_style_comment_start,
+ "\t@ 0x%lx", value_in_comment);
return;
}
/* No match. */
- func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
+ func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_16BIT,
+ (unsigned) given);
return;
}
{
const struct opcode32 *insn;
void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
- bfd_boolean is_mve = is_mve_architecture (info);
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+ bool is_mve = is_mve_architecture (info);
+ enum disassembler_style base_style = dis_style_mnemonic;
+ enum disassembler_style old_base_style = base_style;
- if (print_insn_coprocessor (pc, info, given, TRUE))
+ if (print_insn_coprocessor (pc, info, given, true))
return;
- if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
+ if (!is_mve && print_insn_neon (info, given, true))
return;
if (is_mve && print_insn_mve (info, given))
return;
+ if (print_insn_cde (info, given, true))
+ return;
+
+ if (print_insn_generic_coprocessor (pc, info, given, true))
+ return;
+
for (insn = thumb32_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
{
- bfd_boolean is_clrm = FALSE;
- bfd_boolean is_unpredictable = FALSE;
+ bool is_clrm = false;
+ bool is_unpredictable = false;
signed long value_in_comment = 0;
const char *c = insn->assembler;
{
if (*c != '%')
{
- func (stream, "%c", *c);
+ if (*c == '@')
+ base_style = dis_style_comment_start;
+ if (*c == '\t')
+ base_style = dis_style_text;
+ func (stream, base_style, "%c", *c);
continue;
}
switch (*++c)
{
+ case '{':
+ ++c;
+ if (*c == '\0')
+ abort ();
+ old_base_style = base_style;
+ base_style = decode_base_style (*c);
+ ++c;
+ if (*c != ':')
+ abort ();
+ break;
+
+ case '}':
+ base_style = old_base_style;
+ break;
+
case '%':
- func (stream, "%%");
+ func (stream, base_style, "%%");
break;
case 'c':
if (ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
+ func (stream, dis_style_mnemonic, "%s",
+ arm_conditional[IFTHEN_COND]);
break;
case 'x':
if (ifthen_next_state)
- func (stream, "\t; unpredictable branch in IT block\n");
+ func (stream, dis_style_comment_start,
+ "\t@ unpredictable branch in IT block\n");
break;
case 'X':
if (ifthen_state)
- func (stream, "\t; unpredictable <IT:%s>",
+ func (stream, dis_style_comment_start,
+ "\t@ unpredictable <IT:%s>",
arm_conditional[IFTHEN_COND]);
break;
imm12 |= (given & 0x000000ffu);
imm12 |= (given & 0x00007000u) >> 4;
imm12 |= (given & 0x04000000u) >> 15;
- func (stream, "#%u", imm12);
+ func (stream, dis_style_immediate, "#%u", imm12);
value_in_comment = imm12;
}
break;
imm8 = (bits & 0x07f) | 0x80;
imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
}
- func (stream, "#%u", imm);
+ func (stream, dis_style_immediate, "#%u", imm);
value_in_comment = imm;
}
break;
imm |= (given & 0x00007000u) >> 4;
imm |= (given & 0x04000000u) >> 15;
imm |= (given & 0x000f0000u) >> 4;
- func (stream, "#%u", imm);
+ func (stream, dis_style_immediate, "#%u", imm);
value_in_comment = imm;
}
break;
imm |= (given & 0x000f0000u) >> 16;
imm |= (given & 0x00000ff0u) >> 0;
imm |= (given & 0x0000000fu) << 12;
- func (stream, "#%u", imm);
+ func (stream, dis_style_immediate, "#%u", imm);
value_in_comment = imm;
}
break;
imm |= (given & 0x000f0000u) >> 4;
imm |= (given & 0x00000fffu) >> 0;
- func (stream, "#%u", imm);
+ func (stream, dis_style_immediate, "#%u", imm);
value_in_comment = imm;
}
break;
imm |= (given & 0x00000fffu);
imm |= (given & 0x000f0000u) >> 4;
- func (stream, "#%u", imm);
+ func (stream, dis_style_immediate, "#%u", imm);
value_in_comment = imm;
}
break;
imm |= (given & 0x000000c0u) >> 6;
imm |= (given & 0x00007000u) >> 10;
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s", arm_regnames[reg]);
switch (stp)
{
case 0:
if (imm > 0)
- func (stream, ", lsl #%u", imm);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "lsl ");
+ func (stream, dis_style_immediate, "#%u", imm);
+ }
break;
case 1:
if (imm == 0)
imm = 32;
- func (stream, ", lsr #%u", imm);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "lsr ");
+ func (stream, dis_style_immediate, "#%u", imm);
break;
case 2:
if (imm == 0)
imm = 32;
- func (stream, ", asr #%u", imm);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "asr ");
+ func (stream, dis_style_immediate, "#%u", imm);
break;
case 3:
if (imm == 0)
- func (stream, ", rrx");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "rrx");
+ }
else
- func (stream, ", ror #%u", imm);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "ror ");
+ func (stream, dis_style_immediate, "#%u", imm);
+ }
}
}
break;
unsigned int op = (given & 0x00000f00) >> 8;
unsigned int i12 = (given & 0x00000fff);
unsigned int i8 = (given & 0x000000ff);
- bfd_boolean writeback = FALSE, postind = FALSE;
+ bool writeback = false, postind = false;
bfd_vma offset = 0;
- func (stream, "[%s", arm_regnames[Rn]);
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s", arm_regnames[Rn]);
if (U) /* 12-bit positive immediate offset. */
{
offset = i12;
unsigned int Rm = (i8 & 0x0f);
unsigned int sh = (i8 & 0x30) >> 4;
- func (stream, ", %s", arm_regnames[Rm]);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_register, "%s",
+ arm_regnames[Rm]);
if (sh)
- func (stream, ", lsl #%u", sh);
- func (stream, "]");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "lsl ");
+ func (stream, dis_style_immediate, "#%u", sh);
+ }
+ func (stream, dis_style_text, "]");
break;
}
else switch (op)
case 0xF: /* 8-bit + preindex with wb. */
offset = i8;
- writeback = TRUE;
+ writeback = true;
break;
case 0xD: /* 8-bit - preindex with wb. */
offset = -i8;
- writeback = TRUE;
+ writeback = true;
break;
case 0xB: /* 8-bit + postindex. */
offset = i8;
- postind = TRUE;
+ postind = true;
break;
case 0x9: /* 8-bit - postindex. */
offset = -i8;
- postind = TRUE;
+ postind = true;
break;
default:
- func (stream, ", <undefined>]");
+ func (stream, dis_style_text, ", <undefined>]");
goto skip;
}
if (postind)
- func (stream, "], #%d", (int) offset);
+ {
+ func (stream, dis_style_text, "], ");
+ func (stream, dis_style_immediate, "#%d", (int) offset);
+ }
else
{
if (offset)
- func (stream, ", #%d", (int) offset);
- func (stream, writeback ? "]!" : "]");
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%d",
+ (int) offset);
+ }
+ func (stream, dis_style_text, writeback ? "]!" : "]");
}
if (Rn == 15)
{
- func (stream, "\t; ");
+ func (stream, dis_style_comment_start, "\t@ ");
info->print_address_func (((pc + 4) & ~3) + offset, info);
}
}
unsigned int Rn = (given & 0x000f0000) >> 16;
unsigned int off = (given & 0x000000ff);
- func (stream, "[%s", arm_regnames[Rn]);
+ func (stream, dis_style_text, "[");
+ func (stream, dis_style_register, "%s", arm_regnames[Rn]);
if (PRE_BIT_SET)
{
if (off || !U)
{
- func (stream, ", #%c%u", U ? '+' : '-', off * 4);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%c%u",
+ U ? '+' : '-', off * 4);
value_in_comment = off * 4 * (U ? 1 : -1);
}
- func (stream, "]");
+ func (stream, dis_style_text, "]");
if (W)
- func (stream, "!");
+ func (stream, dis_style_text, "!");
}
else
{
- func (stream, "], ");
+ func (stream, dis_style_text, "], ");
if (W)
{
- func (stream, "#%c%u", U ? '+' : '-', off * 4);
+ func (stream, dis_style_immediate, "#%c%u",
+ U ? '+' : '-', off * 4);
value_in_comment = off * 4 * (U ? 1 : -1);
}
else
{
- func (stream, "{%u}", off);
+ func (stream, dis_style_text, "{");
+ func (stream, dis_style_immediate, "%u", off);
+ func (stream, dis_style_text, "}");
value_in_comment = off;
}
}
switch (type)
{
- case 0: func (stream, Sbit ? "sb" : "b"); break;
- case 1: func (stream, Sbit ? "sh" : "h"); break;
+ case 0:
+ func (stream, dis_style_mnemonic, Sbit ? "sb" : "b");
+ break;
+ case 1:
+ func (stream, dis_style_mnemonic, Sbit ? "sh" : "h");
+ break;
case 2:
if (Sbit)
- func (stream, "??");
+ func (stream, dis_style_text, "??");
break;
case 3:
- func (stream, "??");
+ func (stream, dis_style_text, "??");
break;
}
}
break;
case 'n':
- is_clrm = TRUE;
+ is_clrm = true;
/* Fall through. */
case 'm':
{
int started = 0;
int reg;
- func (stream, "{");
+ func (stream, dis_style_text, "{");
for (reg = 0; reg < 16; reg++)
if ((given & (1 << reg)) != 0)
{
if (started)
- func (stream, ", ");
+ func (stream, dis_style_text, ", ");
started = 1;
if (is_clrm && reg == 13)
- func (stream, "(invalid: %s)", arm_regnames[reg]);
+ func (stream, dis_style_text, "(invalid: %s)",
+ arm_regnames[reg]);
else if (is_clrm && reg == 15)
- func (stream, "%s", "APSR");
+ func (stream, dis_style_register, "%s", "APSR");
else
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[reg]);
}
- func (stream, "}");
+ func (stream, dis_style_text, "}");
}
break;
lsb |= (given & 0x000000c0u) >> 6;
lsb |= (given & 0x00007000u) >> 10;
- func (stream, "#%u, #%u", lsb, msb - lsb + 1);
+ func (stream, dis_style_immediate, "#%u", lsb);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%u", msb - lsb + 1);
}
break;
lsb |= (given & 0x000000c0u) >> 6;
lsb |= (given & 0x00007000u) >> 10;
- func (stream, "#%u, #%u", lsb, width);
+ func (stream, dis_style_immediate, "#%u", lsb);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "#%u", width);
}
break;
case 'G':
{
unsigned int boff = (((given & 0x07800000) >> 23) << 1);
- func (stream, "%x", boff);
+ func (stream, dis_style_immediate, "%x", boff);
}
break;
unsigned int T = (given & 0x00020000u) >> 17;
unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
unsigned int boffset = (T == 1) ? 4 : 2;
- func (stream, ", ");
- func (stream, "%x", endoffset + boffset);
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_immediate, "%x",
+ endoffset + boffset);
}
break;
offset |= (given & 0x000007ff) << 1;
offset -= (1 << 20);
- info->print_address_func (pc + 4 + offset, info);
+ bfd_vma target = pc + 4 + offset;
+ info->print_address_func (target, info);
+
+ /* Fill in instruction information. */
+ info->insn_info_valid = 1;
+ info->insn_type = dis_branch;
+ info->target = target;
}
break;
offset &= ~2u;
info->print_address_func (offset, info);
+
+ /* Fill in instruction information. */
+ info->insn_info_valid = 1;
+ info->insn_type = dis_branch;
+ info->target = offset;
}
break;
shift |= (given & 0x000000c0u) >> 6;
shift |= (given & 0x00007000u) >> 10;
if (WRITEBACK_BIT_SET)
- func (stream, ", asr #%u", shift);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "asr ");
+ func (stream, dis_style_immediate, "#%u", shift);
+ }
else if (shift)
- func (stream, ", lsl #%u", shift);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "lsl ");
+ func (stream, dis_style_immediate, "#%u", shift);
+ }
/* else print nothing - lsl #0 */
}
break;
unsigned int rot = (given & 0x00000030) >> 4;
if (rot)
- func (stream, ", ror #%u", rot * 8);
+ {
+ func (stream, dis_style_text, ", ");
+ func (stream, dis_style_sub_mnemonic, "ror ");
+ func (stream, dis_style_immediate, "#%u", rot * 8);
+ }
}
break;
{
switch (given & 0xf)
{
- case 0xf: func (stream, "sy"); break;
- default:
- func (stream, "#%d", (int) given & 0xf);
- break;
+ case 0xf:
+ func (stream, dis_style_sub_mnemonic, "sy");
+ break;
+ default:
+ func (stream, dis_style_immediate, "#%d",
+ (int) given & 0xf);
+ break;
}
}
else
{
const char * opt = data_barrier_option (given & 0xf);
if (opt != NULL)
- func (stream, "%s", opt);
+ func (stream, dis_style_sub_mnemonic, "%s", opt);
else
- func (stream, "#%d", (int) given & 0xf);
+ func (stream, dis_style_immediate, "#%d",
+ (int) given & 0xf);
}
break;
case 'C':
if ((given & 0xff) == 0)
{
- func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
+ func (stream, dis_style_register, "%cPSR_",
+ (given & 0x100000) ? 'S' : 'C');
+
if (given & 0x800)
- func (stream, "f");
+ func (stream, dis_style_register, "f");
if (given & 0x400)
- func (stream, "s");
+ func (stream, dis_style_register, "s");
if (given & 0x200)
- func (stream, "x");
+ func (stream, dis_style_register, "x");
if (given & 0x100)
- func (stream, "c");
+ func (stream, dis_style_register, "c");
}
else if ((given & 0x20) == 0x20)
{
name = banked_regname (sysm);
if (name != NULL)
- func (stream, "%s", name);
+ func (stream, dis_style_register, "%s", name);
else
- func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
+ func (stream, dis_style_text,
+ "(UNDEF: %lu)", (unsigned long) sysm);
}
else
{
- func (stream, "%s", psr_name (given & 0xff));
+ func (stream, dis_style_register, "%s",
+ psr_name (given & 0xff));
}
break;
name = banked_regname (sm);
if (name != NULL)
- func (stream, "%s", name);
+ func (stream, dis_style_register, "%s", name);
else
- func (stream, "(UNDEF: %lu)", (unsigned long) sm);
+ func (stream, dis_style_text,
+ "(UNDEF: %lu)", (unsigned long) sm);
}
else
- func (stream, "%s", psr_name (given & 0xff));
+ func (stream, dis_style_register, "%s",
+ psr_name (given & 0xff));
break;
case '0': case '1': case '2': case '3': case '4':
{
case 's':
if (val <= 3)
- func (stream, "%s", mve_vec_sizename[val]);
+ func (stream, dis_style_mnemonic, "%s",
+ mve_vec_sizename[val]);
else
- func (stream, "<undef size>");
+ func (stream, dis_style_text, "<undef size>");
break;
case 'd':
- func (stream, "%lu", val);
+ func (stream, base_style, "%lu", val);
value_in_comment = val;
break;
case 'D':
- func (stream, "%lu", val + 1);
+ func (stream, dis_style_immediate, "%lu", val + 1);
value_in_comment = val + 1;
break;
case 'W':
- func (stream, "%lu", val * 4);
+ func (stream, dis_style_immediate, "%lu", val * 4);
value_in_comment = val * 4;
break;
case 'S':
if (val == 13)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'R':
if (val == 15)
- is_unpredictable = TRUE;
+ is_unpredictable = true;
/* Fall through. */
case 'r':
- func (stream, "%s", arm_regnames[val]);
+ func (stream, dis_style_register, "%s",
+ arm_regnames[val]);
break;
case 'c':
- func (stream, "%s", arm_conditional[val]);
+ func (stream, base_style, "%s", arm_conditional[val]);
break;
case '\'':
c++;
if (val == ((1ul << width) - 1))
- func (stream, "%c", *c);
+ func (stream, base_style, "%c", *c);
break;
case '`':
c++;
if (val == 0)
- func (stream, "%c", *c);
+ func (stream, dis_style_immediate, "%c", *c);
break;
case '?':
- func (stream, "%c", c[(1 << width) - (int) val]);
+ func (stream, dis_style_mnemonic, "%c",
+ c[(1 << width) - (int) val]);
c += 1 << width;
break;
case 'x':
- func (stream, "0x%lx", val & 0xffffffffUL);
+ func (stream, dis_style_immediate, "0x%lx",
+ val & 0xffffffffUL);
break;
default:
if ((given & (1 << 23)) == 0)
offset = - offset;
- func (stream, "\t; ");
+ func (stream, dis_style_comment_start, "\t@ ");
info->print_address_func ((pc & ~3) + 4 + offset, info);
}
break;
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, dis_style_comment_start, "\t@ 0x%lx",
+ value_in_comment);
if (is_unpredictable)
- func (stream, UNPREDICTABLE_INSTRUCTION);
+ func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
return;
}
/* No match. */
- func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
+ func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
+ (unsigned) given);
return;
}
struct disassemble_info *info,
long given)
{
+ fprintf_styled_ftype func = info->fprintf_styled_func;
+
switch (info->bytes_per_chunk)
{
case 1:
- info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
+ func (info->stream, dis_style_assembler_directive, ".byte");
+ func (info->stream, dis_style_text, "\t");
+ func (info->stream, dis_style_immediate, "0x%02lx", given);
break;
case 2:
- info->fprintf_func (info->stream, ".short\t0x%04lx", given);
+ func (info->stream, dis_style_assembler_directive, ".short");
+ func (info->stream, dis_style_text, "\t");
+ func (info->stream, dis_style_immediate, "0x%04lx", given);
break;
case 4:
- info->fprintf_func (info->stream, ".word\t0x%08lx", given);
+ func (info->stream, dis_style_assembler_directive, ".word");
+ func (info->stream, dis_style_text, "\t");
+ func (info->stream, dis_style_immediate, "0x%08lx", given);
break;
default:
abort ();
Also disallow private symbol, with __tagsym$$ prefix,
from ARM RVCT toolchain being displayed. */
-bfd_boolean
+bool
arm_symbol_is_valid (asymbol * sym,
struct disassemble_info * info ATTRIBUTE_UNUSED)
{
const char * name;
if (sym == NULL)
- return FALSE;
+ return false;
name = bfd_asymbol_name (sym);
{
const char *opt;
+ force_thumb = false;
FOR_EACH_DISASSEMBLER_OPTION (opt, options)
{
- if (CONST_STRNEQ (opt, "reg-names-"))
+ if (startswith (opt, "reg-names-"))
{
unsigned int i;
for (i = 0; i < NUM_ARM_OPTIONS; i++)
opcodes_error_handler (_("unrecognised register name set: %s"),
opt);
}
- else if (CONST_STRNEQ (opt, "force-thumb"))
+ else if (startswith (opt, "force-thumb"))
force_thumb = 1;
- else if (CONST_STRNEQ (opt, "no-force-thumb"))
+ else if (startswith (opt, "no-force-thumb"))
force_thumb = 0;
+ else if (startswith (opt, "coproc"))
+ {
+ const char *procptr = opt + sizeof ("coproc") - 1;
+ char *endptr;
+ uint8_t coproc_number = strtol (procptr, &endptr, 10);
+ if (endptr != procptr + 1 || coproc_number > 7)
+ {
+ opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
+ opt);
+ continue;
+ }
+ if (*endptr != '=')
+ {
+ opcodes_error_handler (_("coproc must have an argument: %s"),
+ opt);
+ continue;
+ }
+ endptr += 1;
+ if (startswith (endptr, "generic"))
+ cde_coprocs &= ~(1 << coproc_number);
+ else if (startswith (endptr, "cde")
+ || startswith (endptr, "CDE"))
+ cde_coprocs |= (1 << coproc_number);
+ else
+ {
+ opcodes_error_handler (
+ _("coprocN argument takes options \"generic\","
+ " \"cde\", or \"CDE\": %s"), opt);
+ }
+ }
else
/* xgettext: c-format */
opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
return;
}
-static bfd_boolean
+static bool
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
enum map_type *map_symbol);
static void
find_ifthen_state (bfd_vma pc,
struct disassemble_info *info,
- bfd_boolean little)
+ bool little)
{
unsigned char b[2];
unsigned int insn;
if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
{
enum map_type type = MAP_ARM;
- bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
+ bool found = mapping_symbol_for_insn (addr, info, &type);
if (!found || (found && type == MAP_THUMB))
{
mapping symbol. */
static int
-is_mapping_symbol (struct disassemble_info *info, int n,
+is_mapping_symbol (struct disassemble_info *info,
+ int n,
enum map_type *map_type)
{
- const char *name;
+ const char *name = bfd_asymbol_name (info->symtab[n]);
- name = bfd_asymbol_name (info->symtab[n]);
- if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
+ if (name[0] == '$'
+ && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
&& (name[2] == 0 || name[2] == '.'))
{
*map_type = ((name[1] == 'a') ? MAP_ARM
: (name[1] == 't') ? MAP_THUMB
: MAP_DATA);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
{
/* If the symbol is in a different section, ignore it. */
if (info->section != NULL && info->section != info->symtab[n]->section)
- return FALSE;
+ return false;
return is_mapping_symbol (info, n, map_type);
}
{
elf_symbol_type *es;
unsigned int type;
+ asymbol * sym;
/* If the symbol is in a different section, ignore it. */
if (info->section != NULL && info->section != info->symtab[n]->section)
- return FALSE;
+ return false;
- es = *(elf_symbol_type **)(info->symtab + n);
+ /* PR 30230: Reject non-ELF symbols, eg synthetic ones. */
+ sym = info->symtab[n];
+ if (bfd_asymbol_flavour (sym) != bfd_target_elf_flavour)
+ return false;
+
+ es = (elf_symbol_type *) sym;
type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
/* If the symbol has function type then use that. */
*map_type = MAP_THUMB;
else
*map_type = MAP_ARM;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Search the mapping symbol state for instruction at pc. This is only
Return TRUE if the mapping state can be determined, and map_symbol
will be updated accordingly. Otherwise, return FALSE. */
-static bfd_boolean
+static bool
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
enum map_type *map_symbol)
{
bfd_vma addr, section_vma = 0;
int n, last_sym = -1;
- bfd_boolean found = FALSE;
- bfd_boolean can_use_search_opt_p = FALSE;
+ bool found = false;
+ bool can_use_search_opt_p = false;
+
+ /* Sanity check. */
+ if (info == NULL)
+ return false;
/* Default to DATA. A text section is required by the ABI to contain an
INSN mapping symbol at the start. A data section has no such
type = MAP_ARM;
struct arm_private_data *private_data;
- if (info->private_data == NULL
+ if (info->private_data == NULL || info->symtab == NULL
+ || info->symtab_size == 0
|| bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
- return FALSE;
+ return false;
private_data = info->private_data;
/* First, look for mapping symbols. */
- if (info->symtab_size != 0)
- {
- if (pc <= private_data->last_mapping_addr)
- private_data->last_mapping_sym = -1;
-
- /* Start scanning at the start of the function, or wherever
- we finished last time. */
- n = info->symtab_pos + 1;
-
- /* If the last stop offset is different from the current one it means we
- are disassembling a different glob of bytes. As such the optimization
- would not be safe and we should start over. */
- can_use_search_opt_p
- = private_data->last_mapping_sym >= 0
- && info->stop_offset == private_data->last_stop_offset;
-
- if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
- n = private_data->last_mapping_sym;
-
- /* Look down while we haven't passed the location being disassembled.
- The reason for this is that there's no defined order between a symbol
- and an mapping symbol that may be at the same address. We may have to
- look at least one position ahead. */
- for (; n < info->symtab_size; n++)
- {
- addr = bfd_asymbol_value (info->symtab[n]);
- if (addr > pc)
- break;
- if (get_map_sym_type (info, n, &type))
- {
- last_sym = n;
- found = TRUE;
- }
- }
+ if (pc <= private_data->last_mapping_addr)
+ private_data->last_mapping_sym = -1;
+
+ /* Start scanning at the start of the function, or wherever
+ we finished last time. */
+ n = info->symtab_pos + 1;
+
+ /* If the last stop offset is different from the current one it means we
+ are disassembling a different glob of bytes. As such the optimization
+ would not be safe and we should start over. */
+ can_use_search_opt_p
+ = (private_data->last_mapping_sym >= 0
+ && info->stop_offset == private_data->last_stop_offset);
+
+ if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
+ n = private_data->last_mapping_sym;
+
+ /* Look down while we haven't passed the location being disassembled.
+ The reason for this is that there's no defined order between a symbol
+ and an mapping symbol that may be at the same address. We may have to
+ look at least one position ahead. */
+ for (; n < info->symtab_size; n++)
+ {
+ addr = bfd_asymbol_value (info->symtab[n]);
+ if (addr > pc)
+ break;
+ if (get_map_sym_type (info, n, &type))
+ {
+ last_sym = n;
+ found = true;
+ }
+ }
- if (!found)
- {
- n = info->symtab_pos;
- if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
- n = private_data->last_mapping_sym;
-
- /* No mapping symbol found at this address. Look backwards
- for a preceeding one, but don't go pass the section start
- otherwise a data section with no mapping symbol can pick up
- a text mapping symbol of a preceeding section. The documentation
- says section can be NULL, in which case we will seek up all the
- way to the top. */
- if (info->section)
- section_vma = info->section->vma;
-
- for (; n >= 0; n--)
- {
- addr = bfd_asymbol_value (info->symtab[n]);
- if (addr < section_vma)
- break;
+ if (!found)
+ {
+ n = info->symtab_pos;
+ if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
+ n = private_data->last_mapping_sym;
+
+ /* No mapping symbol found at this address. Look backwards
+ for a preceeding one, but don't go pass the section start
+ otherwise a data section with no mapping symbol can pick up
+ a text mapping symbol of a preceeding section. The documentation
+ says section can be NULL, in which case we will seek up all the
+ way to the top. */
+ if (info->section)
+ section_vma = info->section->vma;
+
+ for (; n >= 0; n--)
+ {
+ addr = bfd_asymbol_value (info->symtab[n]);
+ if (addr < section_vma)
+ break;
- if (get_map_sym_type (info, n, &type))
- {
- last_sym = n;
- found = TRUE;
- break;
- }
- }
- }
- }
+ if (get_map_sym_type (info, n, &type))
+ {
+ last_sym = n;
+ found = true;
+ break;
+ }
+ }
+ }
/* If no mapping symbol was found, try looking up without a mapping
symbol. This is done by walking up from the current PC to the nearest
if (n >= 0 && get_sym_code_type (info, n, &type))
{
last_sym = n;
- found = TRUE;
+ found = true;
}
}
case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
case bfd_mach_arm_8:
{
- /* Add bits for extensions that Armv8.5-A recognizes. */
- arm_feature_set armv8_5_ext_fset
+ /* Add bits for extensions that Armv8.6-A recognizes. */
+ arm_feature_set armv8_6_ext_fset
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
- ARM_SET_FEATURES (ARM_ARCH_V8_5A);
- ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
+ ARM_SET_FEATURES (ARM_ARCH_V8_6A);
+ ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
break;
}
case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
case bfd_mach_arm_8_1M_MAIN:
ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
+ arm_feature_set mve_all
+ = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
+ ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
force_thumb = 1;
break;
+ case bfd_mach_arm_9: ARM_SET_FEATURES (ARM_ARCH_V9A); break;
/* If the machine type is unknown allow all architecture types and all
- extensions. */
- case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
+ extensions, with the exception of MVE as that clashes with NEON. */
+ case bfd_mach_arm_unknown:
+ ARM_SET_FEATURES (ARM_ARCH_UNKNOWN);
+ break;
default:
abort ();
}
the relevant number of data bytes exist. */
static int
-print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
+print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
{
unsigned char b[4];
- long given;
- int status;
- int is_thumb = FALSE;
- int is_data = FALSE;
- int little_code;
+ unsigned long given;
+ int status;
+ int is_thumb = false;
+ int is_data = false;
+ int little_code;
unsigned int size = 4;
- void (*printer) (bfd_vma, struct disassemble_info *, long);
- bfd_boolean found = FALSE;
+ void (*printer) (bfd_vma, struct disassemble_info *, long);
+ bool found = false;
struct arm_private_data *private_data;
+ /* Clear instruction information field. */
+ info->insn_info_valid = 0;
+ info->branch_delay_insns = 0;
+ info->data_size = 0;
+ info->insn_type = dis_noninsn;
+ info->target = 0;
+ info->target2 = 0;
+
if (info->disassembler_options)
{
parse_arm_disassembler_options (info->disassembler_options);
}
if (force_thumb)
- is_thumb = TRUE;
+ is_thumb = true;
if (is_data)
info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
if (little_code)
- given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
+ given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
else
- given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
+ given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
}
else
{
&& (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
info->endian_code = BFD_ENDIAN_LITTLE;
- return print_insn (pc, info, FALSE);
+ return print_insn (pc, info, false);
}
int
print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
{
- return print_insn (pc, info, TRUE);
+ return print_insn (pc, info, true);
}
const disasm_options_and_args_t *
projects / binutils-gdb.git / blobdiff