/* Declarations for C-SKY opcode table
- Copyright (C) 2007-2019 Free Software Foundation, Inc.
+ Copyright (C) 2007-2022 Free Software Foundation, Inc.
Contributed by C-SKY Microsystems and Mentor Graphics.
This file is part of the GNU opcodes library.
02110-1301, USA. */
#include "opcode/csky.h"
+#include "safe-ctype.h"
#define OP_TABLE_NUM 2
-#define MAX_OPRND_NUM 4
+#define MAX_OPRND_NUM 5
enum operand_type
{
OPRND_TYPE_AREG_WITH_LSHIFT_FPU,
OPRND_TYPE_FREG_WITH_INDEX,
+ OPRND_TYPE_VREG_WITH_INDEX,
/* r1 only, for xtrb0(1)(2)(3) in csky v1 ISA. */
OPRND_TYPE_REG_r1a,
/* r1 only, for divs/divu in csky v1 ISA. */
OPRND_TYPE_IMM5b,
OPRND_TYPE_IMM7b,
OPRND_TYPE_IMM8b,
+ OPRND_TYPE_IMM9b,
OPRND_TYPE_IMM12b,
OPRND_TYPE_IMM15b,
OPRND_TYPE_IMM16b,
/* OPRND_TYPE_IMM5b_a_b means: Immediate in (a, b). */
OPRND_TYPE_IMM5b_1_31,
OPRND_TYPE_IMM5b_7_31,
+ /* OPRND_TYPE_IMM5b_LS means: Imm <= prev Imm. */
+ OPRND_TYPE_IMM5b_LS,
/* Operand type for rori and rotri. */
OPRND_TYPE_IMM5b_RORI,
+ OPRND_TYPE_IMM5b_VSH,
OPRND_TYPE_IMM5b_POWER,
OPRND_TYPE_IMM5b_7_31_POWER,
OPRND_TYPE_IMM5b_BMASKI,
/* Single float and double float. */
OPRND_TYPE_SFLOAT,
OPRND_TYPE_DFLOAT,
+ OPRND_TYPE_HFLOAT_FMOVI,
+ OPRND_TYPE_SFLOAT_FMOVI,
+ OPRND_TYPE_DFLOAT_FMOVI,
};
/* Operand descriptors. */
union csky_operand
{
- struct operand oprnds[5];
+ struct operand oprnds[MAX_OPRND_NUM];
struct suboperand1
{
struct operand oprnd;
/* Encodings for 32-bit opcodes. */
struct csky_opcode_info op32[OP_TABLE_NUM];
/* Instruction set flag. */
- unsigned int isa_flag16;
- unsigned int isa_flag32;
+ uint64_t isa_flag16;
+ uint64_t isa_flag32;
/* Whether this insn needs relocation, 0: no, !=0: yes. */
signed int reloc16;
signed int reloc32;
signed int relax;
/* Worker function to call when this instruction needs special assembler
handling. */
- bfd_boolean (*work)(void);
+ bool (*work) (void);
};
/* The following are the opcodes used in relax/fix process. */
#define OPRND_MASK_2_5 0x3c
#define OPRND_MASK_3_7 0xf8
#define OPRND_MASK_4 0x10
+#define OPRND_MASK_4_5 0x30
#define OPRND_MASK_4_6 0x70
#define OPRND_MASK_4_7 0xf0
#define OPRND_MASK_4_8 0x1f0
#define OPRND_MASK_5_7 0xe0
#define OPRND_MASK_5_8 0x1e0
#define OPRND_MASK_5_9 0x3e0
+#define OPRND_MASK_6 0x40
+#define OPRND_MASK_6_7 0xc0
+#define OPRND_MASK_6_8 0x1c0
#define OPRND_MASK_6_9 0x3c0
#define OPRND_MASK_6_10 0x7c0
+#define OPRND_MASK_7 0x80
+#define OPRND_MASK_7_8 0x180
#define OPRND_MASK_8_9 0x300
#define OPRND_MASK_8_10 0x700
#define OPRND_MASK_8_11 0xf00
#define OPRND_MASK_16_19 0xf0000
#define OPRND_MASK_16_20 0x1f0000
#define OPRND_MASK_16_25 0x3ff0000
+#define OPRND_MASK_17_24 0x1fe0000
+#define OPRND_MASK_20 0x0100000
+#define OPRND_MASK_20_21 0x0300000
+#define OPRND_MASK_20_22 0x0700000
+#define OPRND_MASK_20_23 0x0f00000
+#define OPRND_MASK_20_24 0x1f00000
+#define OPRND_MASK_20_25 0x3f00000
#define OPRND_MASK_21_24 0x1e00000
#define OPRND_MASK_21_25 0x3e00000
#define OPRND_MASK_25 0x2000000
#define OPRND_MASK_RSV 0xffffffff
+#define OPRND_MASK_0_3or5_8 OPRND_MASK_0_3 | OPRND_MASK_5_8
+#define OPRND_MASK_0_3or6_7 OPRND_MASK_0_3 | OPRND_MASK_6_7
#define OPRND_MASK_0_3or21_24 OPRND_MASK_0_3 | OPRND_MASK_21_24
+#define OPRND_MASK_0_3or25 OPRND_MASK_0_3 | OPRND_MASK_25
+#define OPRND_MASK_0_4or21_24 OPRND_MASK_0_4 | OPRND_MASK_21_24
#define OPRND_MASK_0_4or21_25 OPRND_MASK_0_4 | OPRND_MASK_21_25
#define OPRND_MASK_0_4or16_20 OPRND_MASK_0_4 | OPRND_MASK_16_20
#define OPRND_MASK_0_4or8_10 OPRND_MASK_0_4 | OPRND_MASK_8_10
#define OPRND_MASK_0_4or8_9 OPRND_MASK_0_4 | OPRND_MASK_8_9
#define OPRND_MASK_0_14or16_20 OPRND_MASK_0_14 | OPRND_MASK_16_20
#define OPRND_MASK_4or5_8 OPRND_MASK_4 | OPRND_MASK_5_8
+#define OPRND_MASK_5or20_21 OPRND_MASK_5 | OPRND_MASK_20_21
+#define OPRND_MASK_5or20_22 OPRND_MASK_5 | OPRND_MASK_20_22
+#define OPRND_MASK_5or20_23 OPRND_MASK_5 | OPRND_MASK_20_23
+#define OPRND_MASK_5or20_24 OPRND_MASK_5 | OPRND_MASK_20_24
+#define OPRND_MASK_5or20_25 OPRND_MASK_5 | OPRND_MASK_20_25
#define OPRND_MASK_5or21_24 OPRND_MASK_5 | OPRND_MASK_21_24
#define OPRND_MASK_2_5or6_9 OPRND_MASK_2_5 | OPRND_MASK_6_9
#define OPRND_MASK_4_6or21_25 OPRND_MASK_4_6 | OPRND_MASK_21_25
#define OPRND_MASK_5_6or21_25 OPRND_MASK_5_6 | OPRND_MASK_21_25
#define OPRND_MASK_5_7or8_10 OPRND_MASK_5_7 | OPRND_MASK_8_10
#define OPRND_MASK_5_9or21_25 OPRND_MASK_5_9 | OPRND_MASK_21_25
+#define OPRND_MASK_8_9or21_25 OPRND_MASK_8_9 | OPRND_MASK_21_25
+#define OPRND_MASK_8_9or16_25 OPRND_MASK_8_9 | OPRND_MASK_16_20 | OPRND_MASK_21_25
#define OPRND_MASK_16_19or21_24 OPRND_MASK_16_19 | OPRND_MASK_21_24
#define OPRND_MASK_16_20or21_25 OPRND_MASK_16_20 | OPRND_MASK_21_25
#define OPRND_MASK_4or9_10or25 OPRND_MASK_4 | OPRND_MASK_9_10 | OPRND_MASK_25
#define OPRND_MASK_4_7or16_24 OPRND_MASK_4_7 | OPRND_MASK_16_20 | OPRND_MASK_21_24
+#define OPRND_MASK_4_6or20 OPRND_MASK_4_6 | OPRND_MASK_20
+#define OPRND_MASK_5_7or20 OPRND_MASK_5_7 | OPRND_MASK_20
+#define OPRND_MASK_4_5or20or25 OPRND_MASK_4 | OPRND_MASK_5 | OPRND_MASK_20 | OPRND_MASK_25
+#define OPRND_MASK_4_6or20or25 OPRND_MASK_4_6 | OPRND_MASK_20 | OPRND_MASK_25
+#define OPRND_MASK_4_7or20or25 OPRND_MASK_4_7 | OPRND_MASK_20 | OPRND_MASK_25
+#define OPRND_MASK_6_9or17_24 OPRND_MASK_6_9 | OPRND_MASK_17_24
+#define OPRND_MASK_6_7or20 OPRND_MASK_6_7 | OPRND_MASK_20
+#define OPRND_MASK_6or20 OPRND_MASK_6 | OPRND_MASK_20
+#define OPRND_MASK_7or20 OPRND_MASK_7 | OPRND_MASK_20
+#define OPRND_MASK_5or8_9or16_25 OPRND_MASK_5 | OPRND_MASK_8_9or16_25
+#define OPRND_MASK_5or8_9or20_25 OPRND_MASK_5 | OPRND_MASK_8_9 | OPRND_MASK_20_25
#define OPERAND_INFO(mask, type, shift) \
{OPRND_MASK_##mask, OPRND_TYPE_##type, shift}
#define V1_REG_SP 0
#define V1_REG_LR 15
-struct csky_reg
+struct psrbit
{
+ int value;
+ int isa;
const char *name;
- int index;
- int flag;
};
-const char *csky_general_reg[] =
+const struct psrbit cskyv1_psr_bits[] =
{
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
- "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
- NULL,
+ {1, 0, "ie"},
+ {2, 0, "fe"},
+ {4, 0, "ee"},
+ {8, 0, "af"},
+ {0, 0, NULL},
};
-/* TODO: optimize. */
-const char *cskyv2_general_alias_reg[] =
+const struct psrbit cskyv2_psr_bits[] =
{
- "a0", "a1", "a2", "a3", "l0", "l1", "l2", "l3",
- "l4", "l5", "l6", "l7", "t0", "t1", "sp", "lr",
- "l8", "l9", "t2", "t3", "t4", "t5", "t6", "t7",
- "t8", "t9", "r26", "r27", "rdb", "gb", "r30", "r31",
- NULL,
+ {8, 0, "ee"},
+ {4, 0, "ie"},
+ {2, 0, "fe"},
+ {1, 0, "af"},
+ {0x10, CSKY_ISA_TRUST, "sie"},
+ {0, 0, NULL},
};
-/* TODO: optimize. */
-const char *cskyv1_general_alias_reg[] =
+#define GENERAL_REG_BANK 0x80000000
+#define REG_SUPPORT_ALL 0xffffffff
+
+/* CSKY register description. */
+struct csky_reg_def
{
- "sp", "r1", "a0", "a1", "a2", "a3", "a4", "a5",
- "fp", "l0", "l1", "l2", "l3", "l4", "gb", "lr",
- NULL,
+ /* The group number for control registers,
+ and set the bank of genaral registers to a special number. */
+ int bank;
+ int regno;
+ /* The name displayed by serial number. */
+ const char *name;
+ /* The name displayed by ABI infomation,
+ used when objdump add option -Mabi-names. */
+ const char *abi_name;
+ /* The flags indicate which arches support the register. */
+ int arch_flag;
+ /* Some registers depend on special features. */
+ char *features;
};
-/* TODO: optimize. */
-const char *csky_fpu_reg[] =
+/* Arch flag. */
+#define ASH(a) (1 << CSKY_ARCH_##a)
+
+/* All arches exclued 801. */
+#define REG_SUPPORT_A (REG_SUPPORT_ALL & ~ASH(801))
+
+/* All arches exclued 801 and 802. */
+#define REG_SUPPORT_B (REG_SUPPORT_ALL & ~(ASH(801) | ASH(802)))
+
+/* All arches exclued 801, 802, 803, 805.*/
+#define REG_SUPPORT_C (REG_SUPPORT_ALL & ~(ASH(801) \
+ | ASH(802) | ASH(803) | ASH(805)))
+
+/* All arches exclued 801, 802, 803, 805, 807, 810. */
+#define REG_SUPPORT_D (REG_SUPPORT_C & ~(ASH(807) | ASH(810)))
+
+/* All arches exclued 807, 810, 860. */
+#define REG_SUPPORT_E (REG_SUPPORT_ALL & ~(ASH(807) | ASH(810) | \
+ ASH(860)))
+
+/* C-SKY V1 general registers table. */
+static struct csky_reg_def csky_abiv1_general_regs[] =
{
- "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
- "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
- "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
- "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
- NULL,
+#define DECLARE_REG(regno, abi_name, support) \
+ {GENERAL_REG_BANK, regno, "r"#regno, abi_name, support, NULL}
+
+ DECLARE_REG (0, "sp", REG_SUPPORT_ALL),
+ DECLARE_REG (1, NULL, REG_SUPPORT_ALL),
+ DECLARE_REG (2, "a0", REG_SUPPORT_ALL),
+ DECLARE_REG (3, "a1", REG_SUPPORT_ALL),
+ DECLARE_REG (4, "a2", REG_SUPPORT_ALL),
+ DECLARE_REG (5, "a3", REG_SUPPORT_ALL),
+ DECLARE_REG (6, "a4", REG_SUPPORT_ALL),
+ DECLARE_REG (7, "a5", REG_SUPPORT_ALL),
+ DECLARE_REG (8, "fp", REG_SUPPORT_ALL),
+ DECLARE_REG (8, "l0", REG_SUPPORT_ALL),
+ DECLARE_REG (9, "l1", REG_SUPPORT_ALL),
+ DECLARE_REG (10, "l2", REG_SUPPORT_ALL),
+ DECLARE_REG (11, "l3", REG_SUPPORT_ALL),
+ DECLARE_REG (12, "l4", REG_SUPPORT_ALL),
+ DECLARE_REG (13, "l5", REG_SUPPORT_ALL),
+ DECLARE_REG (14, "gb", REG_SUPPORT_ALL),
+ DECLARE_REG (15, "lr", REG_SUPPORT_ALL),
+#undef DECLARE_REG
+ {-1, -1, NULL, NULL, 0, NULL},
};
-/* Control Registers. */
-struct csky_reg csky_ctrl_regs[] =
+/* C-SKY V1 control registers table. */
+static struct csky_reg_def csky_abiv1_control_regs[] =
{
- {"psr", 0, 0}, {"vbr", 1, 0}, {"epsr", 2, 0}, {"fpsr", 3, 0},
- {"epc", 4, 0}, {"fpc", 5, 0}, {"ss0", 6, 0}, {"ss1", 7, 0},
- {"ss2", 8, 0}, {"ss3", 9, 0}, {"ss4", 10, 0}, {"gcr", 11, 0},
- {"gsr", 12, 0}, {"cpuidr", 13, 0}, {"dcsr", 14, 0}, {"cwr", 15, 0},
- {"cfr", 16, 0}, {"ccr", 17, 0}, {"capr", 19, 0}, {"pacr", 20, 0},
- {"rid", 21, 0}, {"sedcr", 8, CSKY_ISA_TRUST}, {"sepcr", 9, CSKY_ISA_TRUST},
- {NULL, 0, 0}
+#define DECLARE_REG(regno, abi_name, support) \
+ {0, regno, "cr"#regno, abi_name, support, NULL}
+
+ DECLARE_REG (0, "psr", REG_SUPPORT_ALL),
+ DECLARE_REG (1, "vbr", REG_SUPPORT_ALL),
+ DECLARE_REG (2, "epsr", REG_SUPPORT_ALL),
+ DECLARE_REG (3, "fpsr", REG_SUPPORT_ALL),
+ DECLARE_REG (4, "epc", REG_SUPPORT_ALL),
+ DECLARE_REG (5, "fpc", REG_SUPPORT_ALL),
+ DECLARE_REG (6, "ss0", REG_SUPPORT_ALL),
+ DECLARE_REG (7, "ss1", REG_SUPPORT_ALL),
+ DECLARE_REG (8, "ss2", REG_SUPPORT_ALL),
+ DECLARE_REG (9, "ss3", REG_SUPPORT_ALL),
+ DECLARE_REG (10, "ss4", REG_SUPPORT_ALL),
+ DECLARE_REG (11, "gcr", REG_SUPPORT_ALL),
+ DECLARE_REG (12, "gsr", REG_SUPPORT_ALL),
+ DECLARE_REG (13, "cpid", REG_SUPPORT_ALL),
+ DECLARE_REG (14, "dcsr", REG_SUPPORT_ALL),
+ DECLARE_REG (15, "cwr", REG_SUPPORT_ALL),
+ DECLARE_REG (16, NULL, REG_SUPPORT_ALL),
+ DECLARE_REG (17, "cfr", REG_SUPPORT_ALL),
+ DECLARE_REG (18, "ccr", REG_SUPPORT_ALL),
+ DECLARE_REG (19, "capr", REG_SUPPORT_ALL),
+ DECLARE_REG (20, "pacr", REG_SUPPORT_ALL),
+ DECLARE_REG (21, "prsr", REG_SUPPORT_ALL),
+ DECLARE_REG (22, "mir", REG_SUPPORT_ALL),
+ DECLARE_REG (23, "mrr", REG_SUPPORT_ALL),
+ DECLARE_REG (24, "mel0", REG_SUPPORT_ALL),
+ DECLARE_REG (25, "mel1", REG_SUPPORT_ALL),
+ DECLARE_REG (26, "meh", REG_SUPPORT_ALL),
+ DECLARE_REG (27, "mcr", REG_SUPPORT_ALL),
+ DECLARE_REG (28, "mpr", REG_SUPPORT_ALL),
+ DECLARE_REG (29, "mwr", REG_SUPPORT_ALL),
+ DECLARE_REG (30, "mcir", REG_SUPPORT_ALL),
+#undef DECLARE_REG
+ {-1, -1, NULL, NULL, 0, NULL},
};
-const char *csky_cp_idx[] =
+/* C-SKY V2 general registers table. */
+static struct csky_reg_def csky_abiv2_general_regs[] =
{
- "cp0", "cp1", "cp2", "cp3", "cp4", "cp5", "cp6", "cp7",
- "cp8", "cp9", "cp10", "cp11", "cp12", "cp13", "cp14", "cp15",
- "cp16", "cp17", "cp18", "cp19", "cp20",
- NULL,
+#ifdef DECLARE_REG
+#undef DECLARE_REG
+#endif
+#define DECLARE_REG(regno, abi_name, support) \
+ {GENERAL_REG_BANK, regno, "r"#regno, abi_name, support, NULL}
+
+ DECLARE_REG (0, "a0", REG_SUPPORT_ALL),
+ DECLARE_REG (1, "a1", REG_SUPPORT_ALL),
+ DECLARE_REG (2, "a2", REG_SUPPORT_ALL),
+ DECLARE_REG (3, "a3", REG_SUPPORT_ALL),
+ DECLARE_REG (4, "l0", REG_SUPPORT_ALL),
+ DECLARE_REG (5, "l1", REG_SUPPORT_ALL),
+ DECLARE_REG (6, "l2", REG_SUPPORT_ALL),
+ DECLARE_REG (7, "l3", REG_SUPPORT_ALL),
+ DECLARE_REG (8, "l4", REG_SUPPORT_ALL),
+ DECLARE_REG (9, "l5", REG_SUPPORT_A),
+ DECLARE_REG (10, "l6", REG_SUPPORT_A),
+ DECLARE_REG (11, "l7", REG_SUPPORT_A),
+ DECLARE_REG (12, "t0", REG_SUPPORT_A),
+ DECLARE_REG (13, "t1", REG_SUPPORT_ALL),
+ DECLARE_REG (14, "sp", REG_SUPPORT_ALL),
+ DECLARE_REG (15, "lr", REG_SUPPORT_ALL),
+ DECLARE_REG (16, "l8", REG_SUPPORT_B),
+ DECLARE_REG (17, "l9", REG_SUPPORT_B),
+ DECLARE_REG (18, "t2", REG_SUPPORT_B),
+ DECLARE_REG (19, "t3", REG_SUPPORT_B),
+ DECLARE_REG (20, "t4", REG_SUPPORT_B),
+ DECLARE_REG (21, "t5", REG_SUPPORT_B),
+ DECLARE_REG (22, "t6", REG_SUPPORT_B),
+ DECLARE_REG (23, "t7", REG_SUPPORT_B),
+ DECLARE_REG (24, "t8", REG_SUPPORT_B),
+ DECLARE_REG (25, "t9", REG_SUPPORT_B),
+ DECLARE_REG (26, NULL, REG_SUPPORT_B),
+ DECLARE_REG (27, NULL, REG_SUPPORT_B),
+ DECLARE_REG (28, "gb", REG_SUPPORT_B),
+ DECLARE_REG (28, "rgb", REG_SUPPORT_B),
+ DECLARE_REG (28, "rdb", REG_SUPPORT_B),
+ DECLARE_REG (29, "tb", REG_SUPPORT_B),
+ DECLARE_REG (29, "rtb", REG_SUPPORT_B),
+ DECLARE_REG (30, "svbr", REG_SUPPORT_A),
+ DECLARE_REG (31, "tls", REG_SUPPORT_B),
+
+ /* The followings JAVA/BCTM's features. */
+ DECLARE_REG (23, "fp", REG_SUPPORT_ALL),
+ DECLARE_REG (24, "top", REG_SUPPORT_ALL),
+ DECLARE_REG (25, "bsp", REG_SUPPORT_ALL),
+
+ {-1, -1, NULL, NULL, 0, NULL},
};
-const char *csky_cp_reg[] =
+/* C-SKY V2 control registers table. */
+static struct csky_reg_def csky_abiv2_control_regs[] =
{
- "cpr0", "cpr1", "cpr2", "cpr3", "cpr4", "cpr5", "cpr6", "cpr7",
- "cpr8", "cpr9", "cpr10", "cpr11", "cpr12", "cpr13", "cpr14", "cpr15",
- "cpr16", "cpr17", "cpr18", "cpr19", "cpr20", "cpr21", "cpr22", "cpr23",
- "cpr24", "cpr25", "cpr26", "cpr27", "cpr28", "cpr29", "cpr30", "cpr31",
- "cpr32", "cpr33", "cpr34", "cpr35", "cpr36", "cpr37", "cpr38", "cpr39",
- "cpr40", "cpr41", "cpr42", "cpr43", "cpr44", "cpr45", "cpr46", "cpr47",
- "cpr48", "cpr49", "cpr50", "cpr51", "cpr52", "cpr53", "cpr54", "cpr55",
- "cpr56", "cpr57", "cpr58", "cpr59", "cpr60", "cpr61", "cpr62", "cpr63",
- NULL,
+
+#ifdef DECLARE_REG
+#undef DECLARE_REG
+#endif
+ /* Bank0. */
+#define DECLARE_REG(regno, abi_name) \
+ {0, regno, "cr<"#regno", 0>", abi_name, REG_SUPPORT_ALL, NULL}
+ DECLARE_REG (0, "psr"),
+ DECLARE_REG (1, "vbr"),
+ DECLARE_REG (2, "epsr"),
+ DECLARE_REG (3, "fpsr"),
+ DECLARE_REG (4, "epc"),
+ DECLARE_REG (5, "fpc"),
+ DECLARE_REG (6, "ss0"),
+ DECLARE_REG (7, "ss1"),
+ DECLARE_REG (8, "ss2"),
+ DECLARE_REG (9, "ss3"),
+ DECLARE_REG (10, "ss4"),
+ DECLARE_REG (11, "gcr"),
+ DECLARE_REG (12, "gsr"),
+ DECLARE_REG (13, "cpid"),
+ DECLARE_REG (14, "dcsr"),
+ DECLARE_REG (15, NULL),
+ DECLARE_REG (16, NULL),
+ DECLARE_REG (17, "cfr"),
+ DECLARE_REG (18, "ccr"),
+ DECLARE_REG (19, "capr"),
+ DECLARE_REG (20, "pacr"),
+ DECLARE_REG (21, "prsr"),
+ DECLARE_REG (22, "cir"),
+ DECLARE_REG (23, "ccr2"),
+ DECLARE_REG (24, NULL),
+ DECLARE_REG (25, "cer2"),
+ DECLARE_REG (26, NULL),
+ DECLARE_REG (27, NULL),
+ DECLARE_REG (28, "rvbr"),
+ DECLARE_REG (29, "rmr"),
+ DECLARE_REG (30, "mpid"),
+
+#undef DECLARE_REG
+#define DECLARE_REG(regno, abi_name, support) \
+ {0, regno, "cr<"#regno", 0>", abi_name, support, NULL}
+ DECLARE_REG (31, "chr", REG_SUPPORT_E),
+ DECLARE_REG (31, "hint", REG_SUPPORT_C),
+
+ /* Bank1. */
+#undef DECLARE_REG
+#define DECLARE_REG(regno, abi_name) \
+ {1, regno, "cr<"#regno", 1>", abi_name, REG_SUPPORT_ALL, NULL}
+
+ DECLARE_REG (14, "usp"),
+ DECLARE_REG (26, "cindex"),
+ DECLARE_REG (27, "cdata0"),
+ DECLARE_REG (28, "cdata1"),
+ DECLARE_REG (29, "cdata2"),
+ DECLARE_REG (30, "cdata3"),
+ DECLARE_REG (31, "cins"),
+
+ /* Bank2. */
+#undef DECLARE_REG
+#define DECLARE_REG(regno, abi_name) \
+ {2, regno, "cr<"#regno", 2>", abi_name, REG_SUPPORT_ALL, NULL}
+
+ DECLARE_REG (0, "fid"),
+ DECLARE_REG (1, "fcr"),
+ DECLARE_REG (2, "fesr"),
+
+ /* Bank3. */
+#undef DECLARE_REG
+#define DECLARE_REG(regno, abi_name) \
+ {3, regno, "cr<"#regno", 3>", abi_name, REG_SUPPORT_ALL, NULL}
+ DECLARE_REG (8, "dcr"),
+ DECLARE_REG (8, "sedcr"),
+ DECLARE_REG (9, "pcr"),
+ DECLARE_REG (9, "sepcr"),
+
+ /* Bank15. */
+#undef DECLARE_REG
+#define DECLARE_REG(regno, abi_name) \
+ {15, regno, "cr<"#regno", 15>", abi_name, REG_SUPPORT_ALL, NULL}
+
+ DECLARE_REG (0, "mir"),
+ DECLARE_REG (2, "mel0"),
+ DECLARE_REG (3, "mel1"),
+ DECLARE_REG (4, "meh"),
+ DECLARE_REG (6, "mpr"),
+ DECLARE_REG (8, "mcir"),
+ DECLARE_REG (28, "mpgd0"),
+ DECLARE_REG (29, "mpgd"),
+ DECLARE_REG (29, "mpgd1"),
+ DECLARE_REG (30, "msa0"),
+ DECLARE_REG (31, "msa1"),
+#undef DECLARE_REG
+ {-1, -1, NULL, NULL, 0, NULL},
};
-const char *csky_cp_creg[] =
+/* Get register name according to giving parameters,
+ IS_ABI controls whether is ABI name or not. */
+static inline const char *
+get_register_name (struct csky_reg_def *reg_table,
+ int arch, int bank, int regno, int is_abi)
{
- "cpcr0", "cpcr1", "cpcr2", "cpcr3",
- "cpcr4", "cpcr5", "cpcr6", "cpcr7",
- "cpcr8", "cpcr9", "cpcr10", "cpcr11",
- "cpcr12", "cpcr13", "cpcr14", "cpcr15",
- "cpcr16", "cpcr17", "cpcr18", "cpcr19",
- "cpcr20", "cpcr21", "cpcr22", "cpcr23",
- "cpcr24", "cpcr25", "cpcr26", "cpcr27",
- "cpcr28", "cpcr29", "cpcr30", "cpcr31",
- "cpcr32", "cpcr33", "cpcr34", "cpcr35",
- "cpcr36", "cpcr37", "cpcr38", "cpcr39",
- "cpcr40", "cpcr41", "cpcr42", "cpcr43",
- "cpcr44", "cpcr45", "cpcr46", "cpcr47",
- "cpcr48", "cpcr49", "cpcr50", "cpcr51",
- "cpcr52", "cpcr53", "cpcr54", "cpcr55",
- "cpcr56", "cpcr57", "cpcr58", "cpcr59",
- "cpcr60", "cpcr61", "cpcr62", "cpcr63",
- NULL,
-};
+ static char regname[64] = {0};
+ unsigned int i = 0;
+ while (reg_table[i].name != NULL)
+ {
+ if (reg_table[i].bank == bank
+ && reg_table[i].regno == regno
+ && (reg_table[i].arch_flag & (1u << (arch & CSKY_ARCH_MASK))))
+ {
+ if (is_abi && reg_table[i].abi_name)
+ return reg_table[i].abi_name;
+ else
+ return reg_table[i].name;
+ }
+ i++;
+ }
-struct psrbit
+ if (bank & 0x80000000)
+ return "unkown register";
+
+ sprintf (regname, "cr<%d, %d>", regno, bank);
+
+ return regname;
+}
+
+/* Get register number according to giving parameters.
+ If not found, return -1. */
+static inline int
+get_register_number (struct csky_reg_def *reg_table,
+ int arch, char *s, char **end, int *bank)
{
- int value;
- int isa;
- const char *name;
-};
-const struct psrbit cskyv1_psr_bits[] =
+ unsigned int i = 0;
+ int len = 0;
+ while (reg_table[i].name != NULL)
+ {
+ len = strlen (reg_table[i].name);
+ if ((strncasecmp (reg_table[i].name, s, len) == 0)
+ && !(ISDIGIT (s[len]))
+ && (reg_table[i].arch_flag & (1u << (arch & CSKY_ARCH_MASK))))
+ {
+ *end = s + len;
+ *bank = reg_table[i].bank;
+ return reg_table[i].regno;
+ }
+
+ if (reg_table[i].abi_name == NULL)
+ {
+ i++;
+ continue;
+ }
+
+ len = strlen (reg_table[i].abi_name);
+ if ((strncasecmp (reg_table[i].abi_name, s, len) == 0)
+ && !(ISALNUM (s[len]))
+ && (reg_table[i].arch_flag & (1u << (arch & CSKY_ARCH_MASK))))
+ {
+ *end = s + len;
+ *bank = reg_table[i].bank;
+ return reg_table[i].regno;
+ }
+ i++;
+ }
+ return -1;
+}
+
+/* Return general register's name. */
+static inline const char *
+csky_get_general_reg_name (int arch, int regno, int is_abi)
{
- {1, 0, "ie"},
- {2, 0, "fe"},
- {4, 0, "ee"},
- {8, 0, "af"},
- {0, 0, NULL},
-};
-const struct psrbit cskyv2_psr_bits[] =
+ struct csky_reg_def *reg_table;
+
+ if (IS_CSKY_ARCH_V1 (arch))
+ reg_table = csky_abiv1_general_regs;
+ else
+ reg_table = csky_abiv2_general_regs;
+
+ return get_register_name (reg_table, arch, GENERAL_REG_BANK, regno, is_abi);
+}
+
+/* Return general register's number. */
+static inline int
+csky_get_general_regno (int arch, char *s, char **end)
{
- {8, 0, "ee"},
- {4, 0, "ie"},
- {2, 0, "fe"},
- {1, 0, "af"},
- {0x10, CSKY_ISA_TRUST, "sie"},
- {0, 0, NULL},
-};
+ struct csky_reg_def *reg_table;
+ int bank = 0;
+
+ if (IS_CSKY_ARCH_V1 (arch))
+ reg_table = csky_abiv1_general_regs;
+ else
+ reg_table = csky_abiv2_general_regs;
+
+ return get_register_number (reg_table, arch, s, end, &bank);
+}
+/* Return control register's name. */
+static inline const char *
+csky_get_control_reg_name (int arch, int bank, int regno, int is_abi)
+{
+ struct csky_reg_def *reg_table;
+
+ if (IS_CSKY_ARCH_V1 (arch))
+ reg_table = csky_abiv1_control_regs;
+ else
+ reg_table = csky_abiv2_control_regs;
+
+ return get_register_name (reg_table, arch, bank, regno, is_abi);
+}
+
+/* Return control register's number. */
+static inline int
+csky_get_control_regno (int arch, char *s, char **end, int *bank)
+{
+ struct csky_reg_def *reg_table;
+
+ if (IS_CSKY_ARCH_V1 (arch))
+ reg_table = csky_abiv1_control_regs;
+ else
+ reg_table = csky_abiv2_control_regs;
+
+ return get_register_number (reg_table, arch, s, end, bank);
+}
/* C-SKY V1 opcodes. */
const struct csky_opcode csky_v1_opcodes[] =
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
OP32 ("mulsws",
- OPCODE_INFO2 (0xc4009480,
+ OPCODE_INFO2 (0xc4009500,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP),
CSKY_ISA_DSP),
OP32 ("mvtc",
OPCODE_INFO0 (0xc4009a00),
- CSKY_ISA_DSP),
+ CSKY_ISA_DSPE60),
OP32 ("mfhi",
OPCODE_INFO1 (0xc4009c20,
(0_4, AREG, OPRND_SHIFT_0_BIT)),
(0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT),
(16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_1E2),
- DOP32 ("sync",
- OPCODE_INFO1 (0xc0000420,
- (21_25, IMM5b, OPRND_SHIFT_0_BIT)),
- OPCODE_INFO0 (0xc0000420),
- CSKYV2_ISA_E1),
DOP32 ("idly",
OPCODE_INFO1 (0xc0001c20,
(21_25, OIMM5b_IDLY, OPRND_SHIFT_0_BIT)),
#undef _TRANSFER
#define _TRANSFER 0
DOP16_DOP32 ("bclri",
- OPCODE_INFO3 (0x3880,
+ OPCODE_INFO2 (0x3880,
(8_10, GREG0_7, OPRND_SHIFT_0_BIT),
- (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(0_4, IMM5b, OPRND_SHIFT_0_BIT)),
- OPCODE_INFO2 (0x3880,
+ OPCODE_INFO3 (0x3880,
(8_10, GREG0_7, OPRND_SHIFT_0_BIT),
+ (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(0_4, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_E1,
OPCODE_INFO3 (0xc4002820,
(21_25, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
DOP16_DOP32 ("bseti",
- OPCODE_INFO3 (0x38a0,
+ OPCODE_INFO2 (0x38a0,
(8_10, GREG0_7, OPRND_SHIFT_0_BIT),
- (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(0_4, IMM5b, OPRND_SHIFT_0_BIT)),
- OPCODE_INFO2 (0x38a0,
+ OPCODE_INFO3 (0x38a0,
(8_10, GREG0_7, OPRND_SHIFT_0_BIT),
+ (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT),
(0_4, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_E1,
OPCODE_INFO3 (0xc4002840,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, IMM5b, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
- DOP16_DOP32 ("addc",
- OPCODE_INFO2 (0x6001,
- (6_9, GREG0_15, OPRND_SHIFT_0_BIT),
- (2_5, GREG0_15, OPRND_SHIFT_0_BIT)),
- OPCODE_INFO3 (0x6001,
- (6_9, GREG0_15, OPRND_SHIFT_0_BIT),
- (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT),
- (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)),
- CSKYV2_ISA_E1,
- OPCODE_INFO3 (0xc4000040,
- (0_4, AREG, OPRND_SHIFT_0_BIT),
- (16_20, AREG, OPRND_SHIFT_0_BIT),
- (21_25, AREG, OPRND_SHIFT_0_BIT)),
- OPCODE_INFO2 (0xc4000040,
- (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT),
- (21_25, AREG, OPRND_SHIFT_0_BIT)),
- CSKYV2_ISA_1E2),
+ DOP16_DOP32_WITH_WORK ("addc",
+ OPCODE_INFO2 (0x6001,
+ (6_9, GREG0_15, OPRND_SHIFT_0_BIT),
+ (2_5, GREG0_15, OPRND_SHIFT_0_BIT)),
+ OPCODE_INFO3 (0x6001,
+ (6_9, GREG0_15, OPRND_SHIFT_0_BIT),
+ (2_5, GREG0_15, OPRND_SHIFT_0_BIT),
+ (2_5, GREG0_15, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_E1,
+ OPCODE_INFO3 (0xc4000040,
+ (0_4, AREG, OPRND_SHIFT_0_BIT),
+ (16_20, AREG, OPRND_SHIFT_0_BIT),
+ (21_25, AREG, OPRND_SHIFT_0_BIT)),
+ OPCODE_INFO2 (0xc4000040,
+ (0_4or16_20, AREG, OPRND_SHIFT_0_BIT),
+ (21_25, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_1E2,
+ v2_work_addc),
DOP16_DOP32 ("subc",
OPCODE_INFO2 (0x6003,
(6_9, GREG0_15, OPRND_SHIFT_0_BIT),
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(5_9, IMM5b, OPRND_SHIFT_0_BIT),
- (21_25, IMM5b, OPRND_SHIFT_0_BIT)),
+ (21_25, IMM5b_LS, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_2E3),
OP32 ("sext",
OPCODE_INFO4 (0xc4005800,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(5_9, IMM5b, OPRND_SHIFT_0_BIT),
- (21_25, IMM5b, OPRND_SHIFT_0_BIT)),
+ (21_25, IMM5b_LS, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_2E3),
#undef _TRANSFER
#define _TRANSFER 2
OPCODE_INFO2 (0xc4009420,
(0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
- CSKY_ISA_DSP),
+ CSKY_ISA_DSPE60),
OP16_OP32 ("ld.b",
SOPCODE_INFO2 (0x8000,
(5_7, GREG0_7, OPRND_SHIFT_0_BIT),
OPCODE_INFO1 (0xe8400000,
(0_15, COND16b, OPRND_SHIFT_1_BIT)),
CSKYV2_ISA_1E2),
+#undef _RELAX
+#undef _RELOC16
+#define _RELAX 0
+#define _RELOC16 0
+ OP32 ("bnezad",
+ OPCODE_INFO2 (0xe8200000,
+ (16_20, AREG, OPRND_SHIFT_0_BIT),
+ (0_15, COND16b, OPRND_SHIFT_1_BIT)),
+ CSKYV2_ISA_3E3R2),
#undef _RELOC16
#undef _RELOC32
-#undef _RELAX
#define _RELOC16 0
#define _RELOC32 0
-#define _RELAX 0
#undef _TRANSFER
#define _TRANSFER 1
OP16_WITH_WORK ("jbr",
#undef _RELAX
#define _RELAX 0
+ /* CK860 instructions. */
+ OP32 ("sync.is",
+ OPCODE_INFO0 (0xc2200420),
+ CSKYV2_ISA_10E60),
+ OP32 ("sync.i",
+ OPCODE_INFO0 (0xc0200420),
+ CSKYV2_ISA_10E60),
+ OP32 ("sync.s",
+ OPCODE_INFO0 (0xc2000420),
+ CSKYV2_ISA_10E60),
+ OP32 ("bar.brwarw",
+ OPCODE_INFO0 (0xc000842f),
+ CSKYV2_ISA_10E60),
+ OP32 ("bar.brwarws",
+ OPCODE_INFO0 (0xc200842f),
+ CSKYV2_ISA_10E60),
+ OP32 ("bar.brar",
+ OPCODE_INFO0 (0xc0008425),
+ CSKYV2_ISA_10E60),
+ OP32 ("bar.brars",
+ OPCODE_INFO0 (0xc2008425),
+ CSKYV2_ISA_10E60),
+ OP32 ("bar.bwaw",
+ OPCODE_INFO0 (0xc000842a),
+ CSKYV2_ISA_10E60),
+ OP32 ("bar.bwaws",
+ OPCODE_INFO0 (0xc200842a),
+ CSKYV2_ISA_10E60),
+ OP32 ("icache.iall",
+ OPCODE_INFO0 (0xc1009020),
+ CSKYV2_ISA_10E60),
+ OP32 ("icache.ialls",
+ OPCODE_INFO0 (0xc3009020),
+ CSKYV2_ISA_10E60),
+ OP32 ("l2cache.iall",
+ OPCODE_INFO0 (0xc1009820),
+ CSKYV2_ISA_10E60),
+ OP32 ("l2cache.call",
+ OPCODE_INFO0 (0xc0809820),
+ CSKYV2_ISA_10E60),
+ OP32 ("l2cache.ciall",
+ OPCODE_INFO0 (0xc1809820),
+ CSKYV2_ISA_10E60),
+ OP32 ("icache.iva",
+ OPCODE_INFO1 (0xc1609020,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("dcache.iall",
+ OPCODE_INFO0 (0xc1009420),
+ CSKYV2_ISA_10E60),
+ OP32 ("dcache.iva",
+ OPCODE_INFO1 (0xc1609420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("dcache.isw",
+ OPCODE_INFO1 (0xc1409420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("dcache.call",
+ OPCODE_INFO0 (0xc0809420),
+ CSKYV2_ISA_10E60),
+ OP32 ("dcache.cva",
+ OPCODE_INFO1 (0xc0e09420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("dcache.cval1",
+ OPCODE_INFO1 (0xc2e09420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("dcache.csw",
+ OPCODE_INFO1 (0xc0c09420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("dcache.ciall",
+ OPCODE_INFO0 (0xc1809420),
+ CSKYV2_ISA_10E60),
+ OP32 ("dcache.civa",
+ OPCODE_INFO1 (0xc1e09420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("dcache.cisw",
+ OPCODE_INFO1 (0xc1c09420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("tlbi.vaa",
+ OPCODE_INFO1 (0xc0408820,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("tlbi.vaas",
+ OPCODE_INFO1 (0xc2408820,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("tlbi.asid",
+ OPCODE_INFO1 (0xc0208820,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("tlbi.asids",
+ OPCODE_INFO1 (0xc2208820,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("tlbi.va",
+ OPCODE_INFO1 (0xc0608820,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("tlbi.vas",
+ OPCODE_INFO1 (0xc2608820,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32 ("tlbi.all",
+ OPCODE_INFO0 (0xc0008820),
+ CSKYV2_ISA_10E60),
+ OP32 ("tlbi.alls",
+ OPCODE_INFO0 (0xc2008820),
+ CSKYV2_ISA_10E60),
+ DOP32 ("sync",
+ OPCODE_INFO0 (0xc0000420),
+ OPCODE_INFO1 (0xc0000420,
+ (21_25, IMM5b, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_E1),
+
/* The followings are enhance DSP instructions. */
- OP32_WITH_WORK ("bloop",
- OPCODE_INFO3 (0xe9c00000,
+ DOP32_WITH_WORK ("bloop",
+ OPCODE_INFO3 (0xe9c00000,
(16_20, AREG, OPRND_SHIFT_0_BIT),
(0_11, BLOOP_OFF12b, OPRND_SHIFT_1_BIT),
(12_15, BLOOP_OFF4b, OPRND_SHIFT_1_BIT)),
- CSKY_ISA_DSP_ENHANCE,
- dsp_work_bloop),
+ OPCODE_INFO2 (0xe9c00000,
+ (16_20, AREG, OPRND_SHIFT_0_BIT),
+ (0_11, BLOOP_OFF12b, OPRND_SHIFT_1_BIT)),
+ CSKY_ISA_DSP_ENHANCE,
+ dsp_work_bloop),
/* The followings are ld/st instructions. */
OP32 ("ldbi.b",
OPCODE_INFO2 (0xd0008000,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
- CSKY_ISA_DSP_ENHANCE),
+ CSKYV2_ISA_3E3R3),
OP32 ("divsl",
OPCODE_INFO3 (0xf800e2e0,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
- CSKY_ISA_DSP_ENHANCE),
+ CSKYV2_ISA_3E3R3),
OP32 ("mulaca.s8",
OPCODE_INFO3 (0xf800e4c0,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP_ENHANCE),
- OP32 ("plsli.u16",
+ OP32 ("plsli.16",
OPCODE_INFO3 (0xf800d400,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, OIMM4b, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP_ENHANCE),
- OP32 ("plsl.u16",
+ OP32 ("plsl.16",
OPCODE_INFO3 (0xf800d440,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
/* The followings are vdsp instructions for ck810. */
OP32 ("vdup.8",
OPCODE_INFO2 (0xf8000e80,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vdup.16",
OPCODE_INFO2 (0xf8100e80,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vdup.32",
OPCODE_INFO2 (0xfa000e80,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmfvr.u8",
OPCODE_INFO2 (0xf8001200,
(0_4, AREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmfvr.u16",
OPCODE_INFO2 (0xf8001220,
(0_4, AREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmfvr.u32",
OPCODE_INFO2 (0xf8001240,
(0_4, AREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmfvr.s8",
OPCODE_INFO2 (0xf8001280,
(0_4, AREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmfvr.s16",
OPCODE_INFO2 (0xf80012a0,
(0_4, AREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmtvr.u8",
OPCODE_INFO2 (0xf8001300,
- (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+ (0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmtvr.u16",
OPCODE_INFO2 (0xf8001320,
- (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+ (0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
+ OP32 ("vins.8",
+ OPCODE_INFO2 (0xf8001400,
+ (0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vins.16",
+ OPCODE_INFO2 (0xf8101400,
+ (0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vins.32",
+ OPCODE_INFO2 (0xfa001400,
+ (0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
OP32 ("vmtvr.u32",
OPCODE_INFO2 (0xf8001340,
- (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+ (0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vldd.8",
SOPCODE_INFO2 (0xf8002000,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldd.16",
SOPCODE_INFO2 (0xf8002100,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldd.32",
SOPCODE_INFO2 (0xf8002200,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldq.8",
SOPCODE_INFO2 (0xf8002400,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldq.16",
SOPCODE_INFO2 (0xf8002500,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldq.32",
SOPCODE_INFO2 (0xf8002600,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstd.8",
SOPCODE_INFO2 (0xf8002800,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstd.16",
SOPCODE_INFO2 (0xf8002900,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstd.32",
SOPCODE_INFO2 (0xf8002a00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstq.8",
SOPCODE_INFO2 (0xf8002c00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstq.16",
SOPCODE_INFO2 (0xf8002d00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstq.32",
SOPCODE_INFO2 (0xf8002e00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldrd.8",
SOPCODE_INFO2 (0xf8003000,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldrd.16",
SOPCODE_INFO2 (0xf8003100,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldrd.32",
SOPCODE_INFO2 (0xf8003200,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldrq.8",
SOPCODE_INFO2 (0xf8003400,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldrq.16",
SOPCODE_INFO2 (0xf8003500,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldrq.32",
SOPCODE_INFO2 (0xf8003600,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstrd.8",
SOPCODE_INFO2 (0xf8003800,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstrd.16",
SOPCODE_INFO2 (0xf8003900,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstrd.32",
SOPCODE_INFO2 (0xf8003a00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstrq.8",
SOPCODE_INFO2 (0xf8003c00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstrq.16",
SOPCODE_INFO2 (0xf8003d00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstrq.32",
SOPCODE_INFO2 (0xf8003e00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
(16_19, VREG, OPRND_SHIFT_0_BIT),
(21_24, VREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
+ OP32 ("vshri.u8",
+ OPCODE_INFO3 (0xf8000600,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.u16",
+ OPCODE_INFO3 (0xf8100600,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.u32",
+ OPCODE_INFO3 (0xfa000600,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.s8",
+ OPCODE_INFO3 (0xf8000610,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.s16",
+ OPCODE_INFO3 (0xf8100610,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.s32",
+ OPCODE_INFO3 (0xfa000610,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.u8.r",
+ OPCODE_INFO3 (0xf8000640,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.u16.r",
+ OPCODE_INFO3 (0xf8100640,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.u32.r",
+ OPCODE_INFO3 (0xfa000640,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.s8.r",
+ OPCODE_INFO3 (0xf8000650,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.s16.r",
+ OPCODE_INFO3 (0xf8100650,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.s32.r",
+ OPCODE_INFO3 (0xfa000650,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshr.s32.r",
+ OPCODE_INFO3 (0xfa0006d0,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
OP32 ("vshr.s32.r",
OPCODE_INFO3 (0xfa0006d0,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
(21_24, VREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
- OP32 ("vcmphs.u8",
- OPCODE_INFO3 (0xf8000800,
+ OP32 ("vshli.u8",
+ OPCODE_INFO3 (0xf8000700,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
- (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
- OP32 ("vcmphs.u16",
- OPCODE_INFO3 (0xf8100800,
+ OP32 ("vshli.u16",
+ OPCODE_INFO3 (0xf8100700,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
- (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
- OP32 ("vcmphs.u32",
- OPCODE_INFO3 (0xfa000800,
+ OP32 ("vshli.u32",
+ OPCODE_INFO3 (0xfa000700,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
- (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
- OP32 ("vcmphs.s8",
- OPCODE_INFO3 (0xf8000810,
+ OP32 ("vshli.s8",
+ OPCODE_INFO3 (0xf8000710,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
- (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
- OP32 ("vcmphs.s16",
- OPCODE_INFO3 (0xf8100810,
+ OP32 ("vshli.s16",
+ OPCODE_INFO3 (0xf8100710,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
- (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
- OP32 ("vcmphs.s32",
- OPCODE_INFO3 (0xfa000810,
+ OP32 ("vshli.s32",
+ OPCODE_INFO3 (0xfa000710,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
- (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
- OP32 ("vcmplt.u8",
- OPCODE_INFO3 (0xf8000820,
+ OP32 ("vshli.u8.s",
+ OPCODE_INFO3 (0xf8000740,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
- (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
- OP32 ("vcmplt.u16",
- OPCODE_INFO3 (0xf8100820,
+ OP32 ("vshli.u16.s",
+ OPCODE_INFO3 (0xf8100740,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
- (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
- OP32 ("vcmplt.u32",
- OPCODE_INFO3 (0xfa000820,
+ OP32 ("vshli.u32.s",
+ OPCODE_INFO3 (0xfa000740,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
- (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
- OP32 ("vcmplt.s8",
- OPCODE_INFO3 (0xf8000830,
+ OP32 ("vshli.s8.s",
+ OPCODE_INFO3 (0xf8000750,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
- (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
- OP32 ("vcmplt.s16",
- OPCODE_INFO3 (0xf8100830,
+ OP32 ("vshli.s16.s",
+ OPCODE_INFO3 (0xf8100750,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
- (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
- OP32 ("vcmplt.s32",
+ OP32 ("vshli.s32.s",
+ OPCODE_INFO3 (0xfa000750,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vcmphs.u8",
+ OPCODE_INFO3 (0xf8000800,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vcmphs.u16",
+ OPCODE_INFO3 (0xf8100800,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vcmphs.u32",
+ OPCODE_INFO3 (0xfa000800,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vcmphs.s8",
+ OPCODE_INFO3 (0xf8000810,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vcmphs.s16",
+ OPCODE_INFO3 (0xf8100810,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vcmphs.s32",
+ OPCODE_INFO3 (0xfa000810,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vcmplt.u8",
+ OPCODE_INFO3 (0xf8000820,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vcmplt.u16",
+ OPCODE_INFO3 (0xf8100820,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vcmplt.u32",
+ OPCODE_INFO3 (0xfa000820,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vcmplt.s8",
+ OPCODE_INFO3 (0xf8000830,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vcmplt.s16",
+ OPCODE_INFO3 (0xf8100830,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vcmplt.s32",
OPCODE_INFO3 (0xfa000830,
(0_3, VREG, OPRND_SHIFT_0_BIT),
(16_19, VREG, OPRND_SHIFT_0_BIT),
(21_24, VREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
+#define OPRND_SHIFT0(mask, type) (mask, type, OPRND_SHIFT_0_BIT)
+#define OPRND_SHIFT1(mask, type) (mask, type, OPRND_SHIFT_1_BIT)
+#define OPRND_SHIFT2(mask, type) (mask, type, OPRND_SHIFT_2_BIT)
+#define OPRND_SHIFT3(mask, type) (mask, type, OPRND_SHIFT_3_BIT)
+#define OPRND_SHIFT4(mask, type) (mask, type, OPRND_SHIFT_4_BIT)
+
+/* The followings are 860 floating instructions. */
+ OP32 ("fadd.16",
+ OPCODE_INFO3 (0xf400c800,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("faddh",
+ OPCODE_INFO3 (0xf400c800,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsub.16",
+ OPCODE_INFO3 (0xf400c820,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsubh",
+ OPCODE_INFO3 (0xf400c820,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmov.16",
+ OPCODE_INFO2 (0xf400c880,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmovh",
+ OPCODE_INFO2 (0xf400c880,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fabs.16",
+ OPCODE_INFO2 (0xf400c8c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fabsh",
+ OPCODE_INFO2 (0xf400c8c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fneg.16",
+ OPCODE_INFO2 (0xf400c8e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnegh",
+ OPCODE_INFO2 (0xf400c8e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmphsz.16",
+ OPCODE_INFO1 (0xf400c900,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpzhsh",
+ OPCODE_INFO1 (0xf400c900,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpltz.16",
+ OPCODE_INFO1 (0xf400c920,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpzlth",
+ OPCODE_INFO1 (0xf400c920,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpnez.16",
+ OPCODE_INFO1 (0xf400c940,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpzneh",
+ OPCODE_INFO1 (0xf400c940,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpuoz.16",
+ OPCODE_INFO1 (0xf400c960,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpzuoh",
+ OPCODE_INFO1 (0xf400c960,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmphs.16",
+ OPCODE_INFO2 (0xf400c980,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmphsh",
+ OPCODE_INFO2 (0xf400c980,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmplt.16",
+ OPCODE_INFO2 (0xf400c9a0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpne.16",
+ OPCODE_INFO2 (0xf400c9c0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpneh",
+ OPCODE_INFO2 (0xf400c9c0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpuo.16",
+ OPCODE_INFO2 (0xf400c9e0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpuoh",
+ OPCODE_INFO2 (0xf400c9e0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmaxnm.16",
+ OPCODE_INFO3 (0xf400cd00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fminnm.16",
+ OPCODE_INFO3 (0xf400cd20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmphz.16",
+ OPCODE_INFO1 (0xf400cd40,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmplsz.16",
+ OPCODE_INFO1 (0xf400cd60,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmul.16",
+ OPCODE_INFO3 (0xf400ca00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmulh",
+ OPCODE_INFO3 (0xf400ca00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmul.16",
+ OPCODE_INFO3 (0xf400ca20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmulh",
+ OPCODE_INFO3 (0xf400ca20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmula.16",
+ OPCODE_INFO3 (0xf400ca80,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmach",
+ OPCODE_INFO3 (0xf400ca80,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmuls.16",
+ OPCODE_INFO3 (0xf400caa0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmsch",
+ OPCODE_INFO3 (0xf400caa0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmuls.16",
+ OPCODE_INFO3 (0xf400cac0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmach",
+ OPCODE_INFO3 (0xf400cac0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmula.16",
+ OPCODE_INFO3 (0xf400cae0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmsch",
+ OPCODE_INFO3 (0xf400cae0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("ffmula.16",
+ OPCODE_INFO3 (0xf400ce00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("ffmuls.16",
+ OPCODE_INFO3 (0xf400ce20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("ffnmula.16",
+ OPCODE_INFO3 (0xf400ce40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("ffnmuls.16",
+ OPCODE_INFO3 (0xf400ce60,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdivh",
+ OPCODE_INFO3 (0xf400cb00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdiv.16",
+ OPCODE_INFO3 (0xf400cb00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("freciph",
+ OPCODE_INFO2 (0xf400cb20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("frecip.16",
+ OPCODE_INFO2 (0xf400cb20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsqrt.16",
+ OPCODE_INFO2 (0xf400cb40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsqrth",
+ OPCODE_INFO2 (0xf400cb40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsel.16",
+ OPCODE_INFO3 (0xf400cf20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ /* Single floating. */
+ OP32 ("fadd.32",
+ OPCODE_INFO3 (0xf4000000,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fadds",
+ OPCODE_INFO3 (0xf4000000,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsub.32",
+ OPCODE_INFO3 (0xf4000020,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsubs",
+ OPCODE_INFO3 (0xf4000020,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmov.32",
+ OPCODE_INFO2 (0xf4000080,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmovs",
+ OPCODE_INFO2 (0xf4000080,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fabs.32",
+ OPCODE_INFO2 (0xf40000c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fabss",
+ OPCODE_INFO2 (0xf40000c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fneg.32",
+ OPCODE_INFO2 (0xf40000e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnegs",
+ OPCODE_INFO2 (0xf40000e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmphsz.32",
+ OPCODE_INFO1 (0xf4000100,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpzhss",
+ OPCODE_INFO1 (0xf4000100,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpltz.32",
+ OPCODE_INFO1 (0xf4000120,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpzlts",
+ OPCODE_INFO1 (0xf4000120,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpnez.32",
+ OPCODE_INFO1 (0xf4000140,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpznes",
+ OPCODE_INFO1 (0xf4000140,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpuoz.32",
+ OPCODE_INFO1 (0xf4000160,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpzuos",
+ OPCODE_INFO1 (0xf4000160,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmphs.32",
+ OPCODE_INFO2 (0xf4000180,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmphss",
+ OPCODE_INFO2 (0xf4000180,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmplt.32",
+ OPCODE_INFO2 (0xf40001a0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmplts",
+ OPCODE_INFO2 (0xf40001a0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpne.32",
+ OPCODE_INFO2 (0xf40001c0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpnes",
+ OPCODE_INFO2 (0xf40001c0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpuo.32",
+ OPCODE_INFO2 (0xf40001e0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpuos",
+ OPCODE_INFO2 (0xf40001e0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmaxnm.32",
+ OPCODE_INFO3 (0xf4000500,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fminnm.32",
+ OPCODE_INFO3 (0xf4000520,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmphz.32",
+ OPCODE_INFO1 (0xf4000540,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmplsz.32",
+ OPCODE_INFO1 (0xf4000560,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmul.32",
+ OPCODE_INFO3 (0xf4000200,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmuls",
+ OPCODE_INFO3 (0xf4000200,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmul.32",
+ OPCODE_INFO3 (0xf4000220,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmuls",
+ OPCODE_INFO3 (0xf4000220,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmula.32",
+ OPCODE_INFO3 (0xf4000280,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmacs",
+ OPCODE_INFO3 (0xf4000280,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmuls.32",
+ OPCODE_INFO3 (0xf40002a0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmscs",
+ OPCODE_INFO3 (0xf40002a0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmuls.32",
+ OPCODE_INFO3 (0xf40002c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmacs",
+ OPCODE_INFO3 (0xf40002c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmula.32",
+ OPCODE_INFO3 (0xf40002e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmscs",
+ OPCODE_INFO3 (0xf40002e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("ffmula.32",
+ OPCODE_INFO3 (0xf4000600,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("ffmuls.32",
+ OPCODE_INFO3 (0xf4000620,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("ffnmula.32",
+ OPCODE_INFO3 (0xf4000640,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("ffnmuls.32",
+ OPCODE_INFO3 (0xf4000660,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdiv.32",
+ OPCODE_INFO3 (0xf4000300,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdivs",
+ OPCODE_INFO3 (0xf4000300,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("frecip.32",
+ OPCODE_INFO2 (0xf4000320,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("frecips",
+ OPCODE_INFO2 (0xf4000320,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsqrt.32",
+ OPCODE_INFO2 (0xf4000340,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsqrts",
+ OPCODE_INFO2 (0xf4000340,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsel.32",
+ OPCODE_INFO3 (0xf4000720,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ /* Double floating. */
+ OP32 ("fadd.64",
+ OPCODE_INFO3 (0xf4000800,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("faddd",
+ OPCODE_INFO3 (0xf4000800,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsub.64",
+ OPCODE_INFO3 (0xf4000820,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsubd",
+ OPCODE_INFO3 (0xf4000820,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmov.64",
+ OPCODE_INFO2 (0xf4000880,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmovd",
+ OPCODE_INFO2 (0xf4000880,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmovx.32",
+ OPCODE_INFO2 (0xf40008a0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fabs.64",
+ OPCODE_INFO2 (0xf40008c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fabsd",
+ OPCODE_INFO2 (0xf40008c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fneg.64",
+ OPCODE_INFO2 (0xf40008e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnegd",
+ OPCODE_INFO2 (0xf40008e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmphsz.64",
+ OPCODE_INFO1 (0xf4000900,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpzhsd",
+ OPCODE_INFO1 (0xf4000900,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpltz.64",
+ OPCODE_INFO1 (0xf4000920,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpzltd",
+ OPCODE_INFO1 (0xf4000920,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpnez.64",
+ OPCODE_INFO1 (0xf4000940,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpzned",
+ OPCODE_INFO1 (0xf4000940,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpuoz.64",
+ OPCODE_INFO1 (0xf4000960,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpzuod",
+ OPCODE_INFO1 (0xf4000960,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmphs.64",
+ OPCODE_INFO2 (0xf4000980,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmphsd",
+ OPCODE_INFO2 (0xf4000980,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmplt.64",
+ OPCODE_INFO2 (0xf40009a0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpltd",
+ OPCODE_INFO2 (0xf40009a0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpne.64",
+ OPCODE_INFO2 (0xf40009c0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpned",
+ OPCODE_INFO2 (0xf40009c0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpuo.64",
+ OPCODE_INFO2 (0xf40009e0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmpuod",
+ OPCODE_INFO2 (0xf40009e0,
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmaxnm.64",
+ OPCODE_INFO3 (0xf4000d00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fminnm.64",
+ OPCODE_INFO3 (0xf4000d20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmphz.64",
+ OPCODE_INFO1 (0xf4000d40,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fcmplsz.64",
+ OPCODE_INFO1 (0xf4000d60,
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmul.64",
+ OPCODE_INFO3 (0xf4000a00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmuld",
+ OPCODE_INFO3 (0xf4000a00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmul.64",
+ OPCODE_INFO3 (0xf4000a20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmuld",
+ OPCODE_INFO3 (0xf4000a20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmula.64",
+ OPCODE_INFO3 (0xf4000a80,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmacd",
+ OPCODE_INFO3 (0xf4000a80,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmuls.64",
+ OPCODE_INFO3 (0xf4000aa0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmscd",
+ OPCODE_INFO3 (0xf4000aa0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmuls.64",
+ OPCODE_INFO3 (0xf4000ac0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmacd",
+ OPCODE_INFO3 (0xf4000ac0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmula.64",
+ OPCODE_INFO3 (0xf4000ae0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmscd",
+ OPCODE_INFO3 (0xf4000ae0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("ffmula.64",
+ OPCODE_INFO3 (0xf4000e00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("ffmuls.64",
+ OPCODE_INFO3 (0xf4000e20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("ffnmula.64",
+ OPCODE_INFO3 (0xf4000e40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("ffnmuls.64",
+ OPCODE_INFO3 (0xf4000e60,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdiv.64",
+ OPCODE_INFO3 (0xf4000b00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdivd",
+ OPCODE_INFO3 (0xf4000b00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("frecip.64",
+ OPCODE_INFO2 (0xf4000b20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("frecipd",
+ OPCODE_INFO2 (0xf4000b20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsqrt.64",
+ OPCODE_INFO2 (0xf4000b40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsqrtd",
+ OPCODE_INFO2 (0xf4000b40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fins.32",
+ OPCODE_INFO2 (0xf4000360,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsel.64",
+ OPCODE_INFO3 (0xf4000f20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ /* SIMD floating. */
+ OP32 ("fadd.f32",
+ OPCODE_INFO3 (0xf4001000,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("faddm",
+ OPCODE_INFO3 (0xf4001000,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsub.f32",
+ OPCODE_INFO3 (0xf4001020,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsubm",
+ OPCODE_INFO3 (0xf4001020,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmov.f32",
+ OPCODE_INFO2 (0xf4001080,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmovm",
+ OPCODE_INFO2 (0xf4001080,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fabs.f32",
+ OPCODE_INFO2 (0xf40010c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fabsm",
+ OPCODE_INFO2 (0xf40010c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fneg.f32",
+ OPCODE_INFO2 (0xf40010e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnegm",
+ OPCODE_INFO2 (0xf40010e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmul.f32",
+ OPCODE_INFO3 (0xf4001200,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmulm",
+ OPCODE_INFO3 (0xf4001200,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmula.f32",
+ OPCODE_INFO3 (0xf4001280,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmuls.f32",
+ OPCODE_INFO3 (0xf40012c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fnmacm",
+ OPCODE_INFO3 (0xf40012c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG),
+ OPRND_SHIFT0 (21_25, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ /* floating formate. */
+ OP32 ("fftoi.f32.s32.rn",
+ OPCODE_INFO2 (0xf4001800,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fstosi.rn",
+ OPCODE_INFO2 (0xf4001800,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f32.s32.rz",
+ OPCODE_INFO2 (0xf4001820,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fstosi.rz",
+ OPCODE_INFO2 (0xf4001820,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f32.s32.rpi",
+ OPCODE_INFO2 (0xf4001840,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fstosi.rpi",
+ OPCODE_INFO2 (0xf4001840,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f32.s32.rni",
+ OPCODE_INFO2 (0xf4001860,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fstosi.rni",
+ OPCODE_INFO2 (0xf4001860,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f32.u32.rn",
+ OPCODE_INFO2 (0xf4001880,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fstoui.rn",
+ OPCODE_INFO2 (0xf4001880,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f32.u32.rz",
+ OPCODE_INFO2 (0xf40018a0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fstoui.rz",
+ OPCODE_INFO2 (0xf40018a0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f32.u32.rpi",
+ OPCODE_INFO2 (0xf40018c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fstoui.rpi",
+ OPCODE_INFO2 (0xf40018c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f32.u32.rni",
+ OPCODE_INFO2 (0xf40018e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fstoui.rni",
+ OPCODE_INFO2 (0xf40018e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f64.s32.rn",
+ OPCODE_INFO2 (0xf4001900,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdtosi.rn",
+ OPCODE_INFO2 (0xf4001900,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f64.s32.rz",
+ OPCODE_INFO2 (0xf4001920,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdtosi.rz",
+ OPCODE_INFO2 (0xf4001920,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f64.s32.rpi",
+ OPCODE_INFO2 (0xf4001940,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdtosi.rpi",
+ OPCODE_INFO2 (0xf4001940,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f64.s32.rni",
+ OPCODE_INFO2 (0xf4001960,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdtosi.rni",
+ OPCODE_INFO2 (0xf4001960,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f64.u32.rn",
+ OPCODE_INFO2 (0xf4001980,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdtoui.rn",
+ OPCODE_INFO2 (0xf4001980,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f64.u32.rz",
+ OPCODE_INFO2 (0xf40019a0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdtoui.rz",
+ OPCODE_INFO2 (0xf40019a0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f64.u32.rpi",
+ OPCODE_INFO2 (0xf40019c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdtoui.rpi",
+ OPCODE_INFO2 (0xf40019c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f64.u32.rni",
+ OPCODE_INFO2 (0xf40019e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdtoui.rni",
+ OPCODE_INFO2 (0xf40019e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f16.s32.rn",
+ OPCODE_INFO2 (0xf4001c00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fhtosi.rn",
+ OPCODE_INFO2 (0xf4001c00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f16.s32.rz",
+ OPCODE_INFO2 (0xf4001c20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fhtosi.rz",
+ OPCODE_INFO2 (0xf4001c20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f16.s32.rpi",
+ OPCODE_INFO2 (0xf4001c40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fhtosi.rpi",
+ OPCODE_INFO2 (0xf4001c40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f16.s32.rni",
+ OPCODE_INFO2 (0xf4001c60,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fhtosi.rni",
+ OPCODE_INFO2 (0xf4001c60,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f16.u32.rn",
+ OPCODE_INFO2 (0xf4001c80,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fhtoui.rn",
+ OPCODE_INFO2 (0xf4001c80,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f16.u32.rz",
+ OPCODE_INFO2 (0xf4001ca0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fhtoui.rz",
+ OPCODE_INFO2 (0xf4001ca0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f16.u32.rpi",
+ OPCODE_INFO2 (0xf4001cc0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fhtoui.rpi",
+ OPCODE_INFO2 (0xf4001cc0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f16.u32.rni",
+ OPCODE_INFO2 (0xf4001ce0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fhtoui.rni",
+ OPCODE_INFO2 (0xf4001ce0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fhtos",
+ OPCODE_INFO2 (0xf4001a40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fhtos.f16",
+ OPCODE_INFO2 (0xf4001a40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fstoh",
+ OPCODE_INFO2 (0xf4001a60,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fstoh.f32",
+ OPCODE_INFO2 (0xf4001a60,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdtos",
+ OPCODE_INFO2 (0xf4001ac0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fdtos.f64",
+ OPCODE_INFO2 (0xf4001ac0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fstod",
+ OPCODE_INFO2 (0xf4001ae0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmfvrh",
+ OPCODE_INFO2 (0xf4001b00,
+ OPRND_SHIFT0 (0_4, AREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmfvr.32.1",
+ OPCODE_INFO2 (0xf4001b20,
+ OPRND_SHIFT0 (0_4, AREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmfvrl",
+ OPCODE_INFO2 (0xf4001b20,
+ OPRND_SHIFT0 (0_4, AREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmtvr.16",
+ OPCODE_INFO2 (0xf4001fa0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, AREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmfvr.16",
+ OPCODE_INFO2 (0xf4001f20,
+ OPRND_SHIFT0 (0_4, AREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmtvrh",
+ OPCODE_INFO2 (0xf4001b40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, AREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmtvr.32.1",
+ OPCODE_INFO2 (0xf4001b60,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, AREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmtvrl",
+ OPCODE_INFO2 (0xf4001b60,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, AREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmtvr.64",
+ OPCODE_INFO3 (0xf4001f80,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, AREG),
+ OPRND_SHIFT0 (21_25, AREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmfvr.64",
+ OPCODE_INFO3 (0xf4001f00,
+ OPRND_SHIFT0 (0_4, AREG),
+ OPRND_SHIFT0 (21_25, AREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmtvr.32.2",
+ OPCODE_INFO3 (0xf4001fc0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, AREG),
+ OPRND_SHIFT0 (21_25, AREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fmfvr.32.2",
+ OPCODE_INFO3 (0xf4001f40,
+ OPRND_SHIFT0 (0_4, AREG),
+ OPRND_SHIFT0 (21_25, AREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ /* flsu. */
+ OP32 ("fld.16",
+ SOPCODE_INFO2 (0xf4002300,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (4_7or21_24,
+ IMM_FLDST,
+ OPRND_SHIFT_1_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fldh",
+ SOPCODE_INFO2 (0xf4002300,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (4_7or21_24,
+ IMM_FLDST,
+ OPRND_SHIFT_1_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fst.16",
+ SOPCODE_INFO2 (0xf4002700,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (4_7or21_24,
+ IMM_FLDST,
+ OPRND_SHIFT_1_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32_WITH_WORK ("fsth",
+ SOPCODE_INFO2 (0xf4002700,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (4_7or21_24,
+ IMM_FLDST,
+ OPRND_SHIFT_1_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fldr16",
+ SOPCODE_INFO2 (0xf4002b00,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fldrh",
+ SOPCODE_INFO2 (0xf4002b00,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fstr.16",
+ SOPCODE_INFO2 (0xf4002f00,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32_WITH_WORK ("fstrh",
+ SOPCODE_INFO2 (0xf4002f00,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fldm.16",
+ OPCODE_INFO2 (0xf4003300,
+ (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT),
+ (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fldmh",
+ OPCODE_INFO2 (0xf4003300,
+ (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT),
+ (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fstm.16",
+ OPCODE_INFO2 (0xf4003700,
+ (0_4or21_24,
+ FREGLIST_DASH,
+ OPRND_SHIFT_0_BIT),
+ (16_20,
+ AREG_WITH_BRACKET,
+ OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32_WITH_WORK ("fstmh",
+ OPCODE_INFO2 (0xf4003700,
+ (0_4or21_24,
+ FREGLIST_DASH,
+ OPRND_SHIFT_0_BIT),
+ (16_20,
+ AREG_WITH_BRACKET,
+ OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fldmu.16",
+ OPCODE_INFO2 (0xf4003380,
+ OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fldmu.h",
+ OPCODE_INFO2 (0xf4003380,
+ OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fstmu.16",
+ OPCODE_INFO2 (0xf4003780,
+ OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32_WITH_WORK ("fstmu.h",
+ OPCODE_INFO2 (0xf4003780,
+ OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fld.32",
+ SOPCODE_INFO2 (0xf4002000,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (4_7or21_24,
+ IMM_FLDST,
+ OPRND_SHIFT_2_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("flds",
+ SOPCODE_INFO2 (0xf4002000,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (4_7or21_24,
+ IMM_FLDST,
+ OPRND_SHIFT_2_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fst.32",
+ SOPCODE_INFO2 (0xf4002400,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (4_7or21_24,
+ IMM_FLDST,
+ OPRND_SHIFT_2_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32_WITH_WORK ("fsts",
+ SOPCODE_INFO2 (0xf4002400,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (4_7or21_24,
+ IMM_FLDST,
+ OPRND_SHIFT_2_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fldr.32",
+ SOPCODE_INFO2 (0xf4002800,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fldrs",
+ SOPCODE_INFO2 (0xf4002800,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fstr.32",
+ SOPCODE_INFO2 (0xf4002c00,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32_WITH_WORK ("fstrs",
+ SOPCODE_INFO2 (0xf4002c00,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fldm.32",
+ OPCODE_INFO2 (0xf4003000,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fldms",
+ OPCODE_INFO2 (0xf4003000,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fstm.32",
+ OPCODE_INFO2 (0xf4003400,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32_WITH_WORK ("fstms",
+ OPCODE_INFO2 (0xf4003400,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fldmu.32",
+ OPCODE_INFO2 (0xf4003080,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fldmu.s",
+ OPCODE_INFO2 (0xf4003080,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fstmu.32",
+ OPCODE_INFO2 (0xf4003480,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32_WITH_WORK ("fstmu.s",
+ OPCODE_INFO2 (0xf4003480,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fld.64",
+ SOPCODE_INFO2 (0xf4002100,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (4_7or21_24,
+ IMM_FLDST,
+ OPRND_SHIFT_2_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fldd",
+ SOPCODE_INFO2 (0xf4002100,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (4_7or21_24,
+ IMM_FLDST,
+ OPRND_SHIFT_2_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fst.64",
+ SOPCODE_INFO2 (0xf4002500,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (4_7or21_24,
+ IMM_FLDST,
+ OPRND_SHIFT_2_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32_WITH_WORK ("fstd",
+ SOPCODE_INFO2 (0xf4002500,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (4_7or21_24,
+ IMM_FLDST,
+ OPRND_SHIFT_2_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fldr.64",
+ SOPCODE_INFO2 (0xf4002900,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fldrd",
+ SOPCODE_INFO2 (0xf4002900,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fstr.64",
+ SOPCODE_INFO2 (0xf4002d00,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32_WITH_WORK ("fstrd",
+ SOPCODE_INFO2 (0xf4002d00,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fldm.64",
+ OPCODE_INFO2 (0xf4003100,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fldmd",
+ OPCODE_INFO2 (0xf4003100,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fstm.64",
+ OPCODE_INFO2 (0xf4003500,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32_WITH_WORK ("fstmd",
+ OPCODE_INFO2 (0xf4003500,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fldmu.64",
+ OPCODE_INFO2 (0xf4003180,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fldmu.d",
+ OPCODE_INFO2 (0xf4003180,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fstmu.64",
+ OPCODE_INFO2 (0xf4003580,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32_WITH_WORK ("fstmu.d",
+ OPCODE_INFO2 (0xf4003580,
+ OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+ OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fldrm",
+ SOPCODE_INFO2 (0xf4002a00,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fstrm",
+ SOPCODE_INFO2 (0xf4002e00,
+ (0_4, FREG, OPRND_SHIFT_0_BIT),
+ BRACKET_OPRND ((16_20,
+ AREG,
+ OPRND_SHIFT_0_BIT),
+ (5_6or21_25,
+ AREG_WITH_LSHIFT_FPU,
+ OPRND_SHIFT_0_BIT))),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fldmm",
+ OPCODE_INFO2 (0xf4003200,
+ (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT),
+ (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32_WITH_WORK ("fstmm",
+ OPCODE_INFO2 (0xf4003600,
+ (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT),
+ (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fstore),
+ OP32 ("fftox.f16.u16",
+ OPCODE_INFO2 (0xf4004000,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftox.f16.s16",
+ OPCODE_INFO2 (0xf4004020,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftox.f16.u32",
+ OPCODE_INFO2 (0xf4004100,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftox.f16.s32",
+ OPCODE_INFO2 (0xf4004120,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftox.f32.u32",
+ OPCODE_INFO2 (0xf4004140,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftox.f32.s32",
+ OPCODE_INFO2 (0xf4004160,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftox.f64.u32",
+ OPCODE_INFO2 (0xf4004180,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftox.f64.s32",
+ OPCODE_INFO2 (0xf40041a0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fxtof.u16.f16",
+ OPCODE_INFO2 (0xf4004800,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fxtof.s16.f16",
+ OPCODE_INFO2 (0xf4004820,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fxtof.u32.f16",
+ OPCODE_INFO2 (0xf4004900,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fxtof.s32.f16",
+ OPCODE_INFO2 (0xf4004920,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fxtof.u32.f32",
+ OPCODE_INFO2 (0xf4004940,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fxtof.s32.f32",
+ OPCODE_INFO2 (0xf4004960,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fxtof.u32.f64",
+ OPCODE_INFO2 (0xf4004980,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fxtof.s32.f64",
+ OPCODE_INFO2 (0xf40049a0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f16.s16",
+ OPCODE_INFO2 (0xf4004220,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f16.u16",
+ OPCODE_INFO2 (0xf4004200,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f16.s32",
+ OPCODE_INFO2 (0xf4004320,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f16.u32",
+ OPCODE_INFO2 (0xf4004300,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f32.s32",
+ OPCODE_INFO2 (0xf4004360,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f32.u32",
+ OPCODE_INFO2 (0xf4004340,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f64.s32",
+ OPCODE_INFO2 (0xf40043a0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftoi.f64.u32",
+ OPCODE_INFO2 (0xf4004380,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fitof.s16.f16",
+ OPCODE_INFO2 (0xf4004a20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fitof.u16.f16",
+ OPCODE_INFO2 (0xf4004a00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fitof.s32.f16",
+ OPCODE_INFO2 (0xf4004b20,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fitof.u32.f16",
+ OPCODE_INFO2 (0xf4004b00,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fitof.s32.f32",
+ OPCODE_INFO2 (0xf4004b60,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsitos",
+ OPCODE_INFO2 (0xf4004b60,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fitof.u32.f32",
+ OPCODE_INFO2 (0xf4004b40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fuitos",
+ OPCODE_INFO2 (0xf4004b40,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fitof.s32.f64",
+ OPCODE_INFO2 (0xf4004ba0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fsitod",
+ OPCODE_INFO2 (0xf4004ba0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fitof.u32.f64",
+ OPCODE_INFO2 (0xf4004b80,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fuitod",
+ OPCODE_INFO2 (0xf4004b80,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftofi.f16.rn",
+ OPCODE_INFO2 (0xf4004400,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftofi.f16.rz",
+ OPCODE_INFO2 (0xf4004420,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftofi.f16.rpi",
+ OPCODE_INFO2 (0xf4004440,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftofi.f16.rni",
+ OPCODE_INFO2 (0xf4004460,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftofi.f32.rn",
+ OPCODE_INFO2 (0xf4004480,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftofi.f32.rz",
+ OPCODE_INFO2 (0xf40044a0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftofi.f32.rpi",
+ OPCODE_INFO2 (0xf40044c0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftofi.f32.rni",
+ OPCODE_INFO2 (0xf40044e0,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftofi.f64.rn",
+ OPCODE_INFO2 (0xf4004500,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftofi.f64.rz",
+ OPCODE_INFO2 (0xf4004520,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftofi.f64.rpi",
+ OPCODE_INFO2 (0xf4004540,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("fftofi.f64.rni",
+ OPCODE_INFO2 (0xf4004560,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (16_20, FREG)),
+ CSKY_ISA_FLOAT_7E60),
+ DOP32_WITH_WORK ("fmovi.16",
+ OPCODE_INFO2 (0xf400e400,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (5or8_9or16_25, HFLOAT_FMOVI)),
+ OPCODE_INFO3 (0xf400e400,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (5or8_9or20_25, IMM9b),
+ OPRND_SHIFT0 (16_19, IMM4b)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fmovi),
+ DOP32_WITH_WORK ("fmovi.32",
+ OPCODE_INFO2 (0xf400e440,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (5or8_9or16_25, SFLOAT_FMOVI)),
+ OPCODE_INFO3 (0xf400e440,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (5or8_9or20_25, IMM9b),
+ OPRND_SHIFT0 (16_19, IMM4b)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fmovi),
+ DOP32_WITH_WORK ("fmovi.64",
+ OPCODE_INFO2 (0xf400e480,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (5or8_9or16_25, DFLOAT_FMOVI)),
+ OPCODE_INFO3 (0xf400e480,
+ OPRND_SHIFT0 (0_4, FREG),
+ OPRND_SHIFT0 (5or8_9or20_25, IMM9b),
+ OPRND_SHIFT0 (16_19, IMM4b)),
+ CSKY_ISA_FLOAT_7E60,
+ float_work_fpuv3_fmovi),
+#undef _RELOC32
+#define _RELOC32 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
+ OP32 ("flrw.32",
+ OPCODE_INFO2 (0xf4003800,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("flrws",
+ OPCODE_INFO2 (0xf4003800,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("flrw.64",
+ OPCODE_INFO2 (0xf4003900,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)),
+ CSKY_ISA_FLOAT_7E60),
+ OP32 ("flrwd",
+ OPCODE_INFO2 (0xf4003900,
+ (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+ (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)),
+ CSKY_ISA_FLOAT_7E60),
+#undef _RELOC32
+#define _RELOC32 0
+
/* The following are aliases for other instructions. */
/* setc -> cmphs r0, r0 */
OP16 ("setc",
OPCODE_INFO1 (0xc4007c40,
(0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)),
CSKYV2_ISA_1E2),
+
{NULL, 0, {}, {}, 0, 0, 0, 0, 0, NULL}
};
projects / binutils-gdb.git / blobdiff