THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006
- Free Software Foundation, Inc.
+ Copyright (C) 1996-2017 Free Software Foundation, Inc.
- This file is part of the GNU Binutils and GDB, the GNU debugger.
+ This file is part of libopcodes.
- This program is free software; you can redistribute it and/or modify
+ This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
#include "symcat.h"
#include "frv-desc.h"
#include "frv-opc.h"
+#include "cgen/basic-modes.h"
#include "opintl.h"
#include "safe-ctype.h"
if (length == 0)
return NULL;
- if (word_length > 32)
+ if (word_length > 8 * sizeof (CGEN_INSN_INT))
abort ();
/* For architectures with insns smaller than the base-insn-bitsize,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
-
+
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
-
+
if (value < minval || value > maxval)
{
sprintf
#if CGEN_INT_INSN_P
{
- int shift;
+ int shift_within_word, shift_to_word, shift;
+ /* How to shift the value to BIT0 of the word. */
+ shift_to_word = total_length - (word_offset + word_length);
+
+ /* How to shift the value to the field within the word. */
if (CGEN_INSN_LSB0_P)
- shift = (word_offset + start + 1) - length;
+ shift_within_word = start + 1 - length;
else
- shift = total_length - (word_offset + start + length);
+ shift_within_word = word_length - start - length;
+
+ /* The total SHIFT, then mask in the value. */
+ shift = shift_to_word + shift_within_word;
*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
}
return 1;
}
- if (word_length > 32)
+ if (word_length > 8 * sizeof (CGEN_INSN_INT))
abort ();
/* For architectures with insns smaller than the insn-base-bitsize,
{
unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
- if (word_length > 32)
+ if (word_length > 8 * sizeof (CGEN_INSN_INT))
abort ();
if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
case FRV_OPERAND_LABEL16 :
{
long value = fields->f_label16;
- value = ((int) (((value) - (pc))) >> (2));
+ value = ((SI) (((value) - (pc))) >> (2));
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, buffer);
}
break;
case FRV_OPERAND_LABEL24 :
{
{
- FLD (f_labelH6) = ((int) (((FLD (f_label24)) - (pc))) >> (20));
- FLD (f_labelL18) = ((((unsigned int) (((FLD (f_label24)) - (pc))) >> (2))) & (262143));
+ FLD (f_labelH6) = ((SI) (((FLD (f_label24)) - (pc))) >> (20));
+ FLD (f_labelL18) = ((((UINT) (((FLD (f_label24)) - (pc))) >> (2))) & (262143));
}
errmsg = insert_normal (cd, fields->f_labelH6, 0|(1<<CGEN_IFLD_SIGNED), 0, 30, 6, 32, total_length, buffer);
if (errmsg)
case FRV_OPERAND_SPR :
{
{
- FLD (f_spr_h) = ((unsigned int) (FLD (f_spr)) >> (6));
+ FLD (f_spr_h) = ((UINT) (FLD (f_spr)) >> (6));
FLD (f_spr_l) = ((FLD (f_spr)) & (63));
}
errmsg = insert_normal (cd, fields->f_spr_h, 0, 0, 30, 6, 32, total_length, buffer);
case FRV_OPERAND_U12 :
{
{
- FLD (f_u12_h) = ((int) (FLD (f_u12)) >> (6));
+ FLD (f_u12_h) = ((SI) (FLD (f_u12)) >> (6));
FLD (f_u12_l) = ((FLD (f_u12)) & (63));
}
errmsg = insert_normal (cd, fields->f_u12_h, 0|(1<<CGEN_IFLD_SIGNED), 0, 17, 6, 32, total_length, buffer);
return length;
}
-cgen_insert_fn * const frv_cgen_insert_handlers[] =
+cgen_insert_fn * const frv_cgen_insert_handlers[] =
{
insert_insn_normal,
};
-cgen_extract_fn * const frv_cgen_extract_handlers[] =
+cgen_extract_fn * const frv_cgen_extract_handlers[] =
{
extract_insn_normal,
};