Replace Vex2Sources and Vex3Sources with VexSources.

[binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 6c48dbc54e62f58370ff127b10ed1e6220dd55a9..08fe068cb062c1072d06ff483ff676f871be34f9 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -102,6 +102,10 @@ enum
   CpuFMA,
   /* FMA4 support required */
   CpuFMA4,
+  /* XOP support required */
+  CpuXOP,
+  /* LWP support required */
+  CpuLWP,
   /* MOVBE Instuction support required */
   CpuMovbe,
   /* EPT Instructions required */
@@ -168,6 +172,8 @@ typedef union i386_cpu_flags
       unsigned int cpupclmul:1;
       unsigned int cpufma:1;
       unsigned int cpufma4:1;
+      unsigned int cpuxop:1;
+      unsigned int cpulwp:1;
       unsigned int cpumovbe:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
@@ -237,6 +243,8 @@ enum
   FWait,
   /* quick test for string instructions */
   IsString,
+  /* quick test for lockable instructions */
+  IsLockable,
   /* fake an extra reg operand for clr, imul and special register
      processing for some instructions.  */
   RegKludge,
@@ -266,6 +274,8 @@ enum
        1: 128bit VEX prefix.
        2: 256bit VEX prefix.
    */
+#define VEX128 1
+#define VEX256 2
   Vex,
   /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
      We use VexNDS on insns with VEX DDS since the register-only source
@@ -273,18 +283,37 @@ enum
   VexNDS,
   /* insn has VEX NDD. Register destination is encoded in Vex prefix. */
   VexNDD,
-  /* insn has VEX W0. */
-  VexW0,
-  /* insn has VEX W1. */
-  VexW1,
+  /* insn has VEX NDD. Register destination is encoded in Vex prefix
+     and one of the operands can access a memory location.  */
+  VexLWP,
+  /* How the VEX.W bit is used:
+     0: Set by the REX.W bit.
+     1: VEX.W0.  Should always be 0.
+     2: VEX.W1.  Should always be 1.
+   */
+#define VEXW0  1
+#define VEXW1  2
+  VexW,
   /* insn has VEX 0x0F opcode prefix. */
   Vex0F,
   /* insn has VEX 0x0F38 opcode prefix. */
   Vex0F38,
   /* insn has VEX 0x0F3A opcode prefix. */
   Vex0F3A,
-  /* insn has VEX prefix with 3 soures. */
-  Vex3Sources,
+  /* insn has XOP 0x08 opcode prefix. */
+  XOP08,
+  /* insn has XOP 0x09 opcode prefix. */
+  XOP09,
+  /* insn has XOP 0x0A opcode prefix. */
+  XOP0A,
+  /* number of VEX source operands:
+     0: < 2 source operands.
+     1: 2 source operands.
+     2: 3 source operands.
+   */
+#define VEX2SOURCES    1
+#define VEX3SOURCES    2
+  VexSources,
   /* instruction has VEX 8 bit imm */
   VexImmExt,
   /* SSE to AVX support required */
@@ -330,6 +359,7 @@ typedef struct i386_opcode_modifier
   unsigned int no_ldsuf:1;
   unsigned int fwait:1;
   unsigned int isstring:1;
+  unsigned int islockable:1;
   unsigned int regkludge:1;
   unsigned int firstxmm0:1;
   unsigned int implicit1stxmm0:1;
@@ -345,12 +375,15 @@ typedef struct i386_opcode_modifier
   unsigned int vex:2;
   unsigned int vexnds:1;
   unsigned int vexndd:1;
-  unsigned int vexw0:1;
-  unsigned int vexw1:1;
+  unsigned int vexlwp:1;
+  unsigned int vexw:2;
   unsigned int vex0f:1;
   unsigned int vex0f38:1;
   unsigned int vex0f3a:1;
-  unsigned int vex3sources:1;
+  unsigned int xop08:1;
+  unsigned int xop09:1;
+  unsigned int xop0a:1;
+  unsigned int vexsources:2;
   unsigned int veximmext:1;
   unsigned int sse2avx:1;
   unsigned int noavx:1;